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PI7C9X110
PCI Express-to-PCI Reversible Bridge
Revision 2.4
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PI7C9X110
PCIe-to-PCI Reversible Bridge
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Page 2 of 145 Pericom Semiconductor November 2007, Revision 2.4
PI7C9X110
PCIe-to-PCI Reversible Bridge
REVISION HISTORY
DATE
09/08/2006 11/21/2006 03/06/2007 05/02/2007
REVISION #
2.0 2.1 2.2 2.3
DESCRIPTION
First release of 9X110 datasheet without revision suffix Removed references to PI7C9X110A Revised ESD ratings in "DC Specifications" section 16.2 Revised table 8-1 in section 8 Address bit[5] corrected to equal 0 Address bit[4] corrected to equal GPIO[3] Revised logos and font types and added Industrial Temp Compliancy
11/02/2007
2.4
PREFACE
The datasheet of PI7C9X110 will be enhanced periodically when updated information is available. The technical information in this datasheet is subject to change without notice. This document describes the functionalities of PI7C9X110 (PCI Express Bridge) and provides technical information for designers to design their hardware using PI7C9X110.
Page 3 of 145 Pericom Semiconductor November 2007, Revision 2.4
PI7C9X110
PCIe-to-PCI Reversible Bridge
TABLE OF CONTENTS
1 INTRODUCTION ........................................................................................................................ 14
1.1 1.2 1.3 PCI EXPRESS FEATURES ............................................................................................................................... 14 PCI / PCI-X FEATURES.................................................................................................................................... 15 GENERAL FEATURES ..................................................................................................................................... 15
2
PIN DEFINITIONS ...................................................................................................................... 16
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 SIGNAL TYPES ................................................................................................................................................. 16 PCI EXPRESS SIGNALS................................................................................................................................... 16 PCI SIGNALS..................................................................................................................................................... 16 MODE SELECT AND STRAPPING SIGNALS ............................................................................................... 18 JTAG BOUNDARY SCAN SIGNALS .............................................................................................................. 18 MISCELLANEOUS SIGNALS.......................................................................................................................... 18 POWER AND GROUND PINS.......................................................................................................................... 19 PIN ASSIGNMENTS ......................................................................................................................................... 19
3
MODE SELECTION AND PIN STRAPPING.......................................................................... 20
3.1 3.2 3.3 FUNCTIONAL MODE SELECTION ................................................................................................................ 20 PCI / PCI-X SELECTION .................................................................................................................................. 20 PIN STRAPPING................................................................................................................................................ 21
4 5
FORWARD AND REVERSE BRIDGING ................................................................................ 22 TRANSPARENT AND NON-TRANSPARENT BRIDGING.................................................. 24
5.1 5.2 TRANSPARENT MODE ................................................................................................................................... 24 NON-TRANSPARENT MODE.......................................................................................................................... 24
6
PCI EXPRESS FUNCTIONAL OVERVIEW........................................................................... 26
6.1 6.2 TLP STRUCTURE ............................................................................................................................................. 26 VIRTUAL ISOCHRONOUS OPERATION....................................................................................................... 26
7
CONFIGURATION REGISTERS.............................................................................................. 26
7.1 CONFIGURATION REGISTER MAP............................................................................................................... 27 7.2 PCI EXPRESS EXTENDED CAPABILITY REGISTER MAP ........................................................................ 30 7.3 CONTROL AND STATUS REGISTER MAP................................................................................................... 31 7.4 PCI CONFIGURATION REGISTERS FOR TRANSPARENT BRIDGE MODE ............................................ 32 7.4.1 VENDOR ID - OFFSET 00h ................................................................................................................ 33 7.4.2 DEVICE ID - OFFSET 00h.................................................................................................................. 33 7.4.3 COMMAND REGISTER - OFFSET 04h .............................................................................................. 33 7.4.4 PRIMARY STATUS REGISTER - OFFSET 04h................................................................................... 34 7.4.5 REVISION ID REGISTER - OFFSET 08h ........................................................................................... 35 7.4.6 CLASS CODE REGISTER - OFFSET 08h ........................................................................................... 35 7.4.7 CACHE LINE SIZE REGISTER - OFFSET 0Ch.................................................................................. 35 7.4.8 PRIMARY LATENCY TIMER REGISTER - OFFSET 0Ch .................................................................. 36 7.4.9 PRIMARY HEADER TYPE REGISTER - OFFSET 0Ch ...................................................................... 36 7.4.10 RESERVED REGISTERS - OFFSET 10h TO 17h................................................................................ 36 7.4.11 PRIMARY BUS NUMBER REGISTER - OFFSET 18h ........................................................................ 36 7.4.12 SECONDARY BUS NUMBER REGISTER - OFFSET 18h .................................................................. 36 7.4.13 SUBORDINATE BUS NUMBER REGISTER - OFFSET 18h .............................................................. 36 7.4.14 SECONDARY LATENCY TIME REGISTER - OFFSET 18h................................................................ 36
Page 4 of 145 Pericom Semiconductor November 2007, Revision 2.4
PI7C9X110
PCIe-to-PCI Reversible Bridge
7.4.15 7.4.16 7.4.17 7.4.18 7.4.19 7.4.20 7.4.21 7.4.22 7.4.23 7.4.24 7.4.25 7.4.26 7.4.27 7.4.28 7.4.29 7.4.30 7.4.31 7.4.32 7.4.33 7.4.34 7.4.35 7.4.36 7.4.37 7.4.38 7.4.39 7.4.40 7.4.41 7.4.42 7.4.43 7.4.44 7.4.45 7.4.46 7.4.47 7.4.48 7.4.49 7.4.50 7.4.51 7.4.52 7.4.53 7.4.54 7.4.55 7.4.56 7.4.57 7.4.58 7.4.59 7.4.60 7.4.61 7.4.62 7.4.63 7.4.64 7.4.65 7.4.66
I/O BASE REGISTER - OFFSET 1Ch.................................................................................................. 37 I/O LIMIT REGISTER - OFFSET 1Ch................................................................................................. 37 SECONDARY STATUS REGISTER - OFFSET 1Ch ............................................................................ 37 MEMORY BASE REGISTER - OFFSET 20h ....................................................................................... 38 MEMORY LIMIT REGISTER - OFFSET 20h ...................................................................................... 38 PREFETCHABLE MEMORY BASE REGISTER - OFFSET 24h......................................................... 38 PREFETCHABLE MEMORY LIMIT REGISTER - OFFSET 24h........................................................ 38 PREFETCHABLE BASE UPPER 32-BIT REGISTER - OFFSET 28h................................................. 40 PREFETCHABLE LIMIT UPPER 32-BIT REGISTER - OFFSET 2Ch............................................... 40 I/O BASE UPPER 16-BIT REGISTER - OFFSET 30h......................................................................... 40 I/O LIMIT UPPER 16-BIT REGISTER - OFFSET 30h........................................................................ 40 CAPABILITY POINTER - OFFSET 34h .............................................................................................. 40 EXPANSION ROM BASE ADDRESS REGISTER - OFFSET 38h ....................................................... 40 INTERRUPT LINE REGISTER - OFFSET 3Ch................................................................................... 40 INTERRUPT PIN REGISTER - OFFSET 3Ch ..................................................................................... 41 BRIDGE CONTROL REGISTER - OFFSET 3Ch ................................................................................ 41 PCI DATA BUFFERING CONTROL REGISTER - OFFSET 40h ....................................................... 42 CHIP CONTROL 0 REGISTER - OFFSET 40h................................................................................... 43 RESERVED REGISTER - OFFSET 44h............................................................................................... 46 ARBITER ENABLE REGISTER - OFFSET 48h................................................................................... 46 ARBITER MODE REGISTER - OFFSET 48h...................................................................................... 46 ARBITER PRIORITY REGISTER - OFFSET 48h ................................................................................ 47 RESERVED REGISTERS - OFFSET 4Ch - 64h .................................................................................. 48 EXPRESS TRANSMITTER/RECEIVER REGISTER - OFFSET 68h.................................................... 48 UPSTREAM MEMORY WRITE FRAGMENT CONTROL REGISTER - OFFSET 68h ....................... 49 RESERVED REGISTER - OFFSET 6Ch .............................................................................................. 49 EEPROM AUTOLOAD CONTROL/STATUS REGISTER - OFFSET 70h........................................... 49 RESERVED REGISTER - OFFSET 74h............................................................................................... 51 GPIO DATA AND CONTROL REGISTER - OFFSET 78h.................................................................. 51 RESERVED REGISTER - OFFSET 7Ch .............................................................................................. 51 PCI-X CAPABILITY ID REGISTER - OFFSET 80h ............................................................................ 51 NEXT CAPABILITY POINTER REGISTER - OFFSET 80h ................................................................ 51 PCI-X SECONDARY STATUS REGISTER - OFFSET 80h.................................................................. 51 PCI-X BRIDGE STATUS REGISTER - OFFSET 84h.......................................................................... 52 UPSTREAM SPLIT TRANSACTION REGISTER - OFFSET 88h ........................................................ 53 DOWNSTREAM SPLIT TRANSACTION REGISTER - OFFSET 8Ch ................................................. 53 POWER MANAGEMENT ID REGISTER - OFFSET 90h.................................................................... 54 NEXT CAPABILITY POINTER REGISTER - OFFSET 90h ................................................................ 54 POWER MANAGEMENT CAPABILITY REGISTER - OFFSET 90h .................................................. 54 POWER MANAGEMENT CONTROL AND STATUS REGISTER - OFFSET 94h .............................. 55 PCI-TO-PCI SUPPORT EXTENSION REGISTER - OFFSET 94h ..................................................... 55 RESERVED REGISTERS - OFFSET 98h - 9Ch .................................................................................. 55 CAPABILITY ID REGISTER - OFFSET A0h....................................................................................... 55 NEXT POINTER REGISTER - OFFSET A0h....................................................................................... 55 SLOT NUMBER REGISTER - OFFSET A0h ....................................................................................... 56 CHASSIS NUMBER REGISTER - OFFSET A0h ................................................................................. 56 SECONDARY CLOCK AND CLKRUN CONTROL REGISTER - OFFSET A4h................................. 56 CAPABILITY ID REGISTER - OFFSET A8h....................................................................................... 57 NEXT POINTER REGISTER - OFFSET A8h....................................................................................... 57 RESERVED REGISTER - OFFSET A8h .............................................................................................. 57 SUBSYSTEM VENDOR ID REGISTER - OFFSET ACh...................................................................... 58 SUBSYSTEM ID REGISTER - OFFSET ACh ...................................................................................... 58
Page 5 of 145 Pericom Semiconductor November 2007, Revision 2.4
PI7C9X110
PCIe-to-PCI Reversible Bridge
7.4.67 7.4.68 7.4.69 7.4.70 7.4.71 7.4.72 7.4.73 7.4.74 7.4.75 7.4.76 7.4.77 7.4.78 7.4.79 7.4.80 7.4.81 7.4.82 7.4.83 7.4.84 7.4.85 7.4.86 7.4.87 7.4.88 7.4.89 7.4.90 7.4.91 7.4.92 7.4.93 7.4.94 7.4.95 7.4.96 7.4.97 7.4.98 7.4.99 7.4.100 7.4.101 7.4.102 7.4.103 7.4.104 7.4.105 7.4.106 7.4.107 7.4.108 7.4.109 7.4.110 7.4.111 7.4.112 7.4.113 7.4.114 7.4.115 7.4.116 7.4.117 7.4.118
PCI EXPRESS CAPABILITY ID REGISTER - OFFSET B0h .............................................................. 58 NEXT CAPABILITY POINTER REGISTER - OFFSET B0h ................................................................ 58 PCI EXPRESS CAPABILITY REGISTER - OFFSET B0h ................................................................... 58 DEVICE CAPABILITY REGISTER - OFFSET B4h............................................................................. 58 DEVICE CONTROL REGISTER - OFFSET B8h................................................................................. 59 DEVICE STATUS REGISTER - OFFSET B8h..................................................................................... 60 LINK CAPABILITY REGISTER - OFFSET BCh ................................................................................. 60 LINK CONTROL REGISTER - OFFSET C0h...................................................................................... 61 LINK STATUS REGISTER - OFFSET C0h.......................................................................................... 61 SLOT CAPABILITY REGISTER - OFFSET C4h ................................................................................. 62 SLOT CONTROL REGISTER - OFFSET C8h ..................................................................................... 62 SLOT STATUS REGISTER - OFFSET C8h ......................................................................................... 63 XPIP CONFIGURATION REGISTER 0 - OFFSET CCh..................................................................... 63 XPIP CONFIGURATION REGISTER 1 - OFFSET D0h ..................................................................... 63 XPIP CONFIGURATION REGISTER 2 - OFFSET D4h ..................................................................... 63 HOT SWAP SWITCH DEBOUNCE COUNTER - OFFSET D4h......................................................... 65 CAPABILITY ID REGISTER - OFFSET D8h ...................................................................................... 65 NEXT POINTER REGISTER - OFFSET D8h ...................................................................................... 65 VPD REGISTER - OFFSET D8h ......................................................................................................... 65 VPD DATA REGISTER - OFFSET DCh.............................................................................................. 65 RESERVED REGISTERS - OFFSET E0h - ECh ................................................................................. 66 MESSAGE SIGNALED INTERRUPTS ID REGISTER - F0h............................................................... 66 NEXT CAPABILITIES POINTER REGISTER - F0h............................................................................ 66 MESSAGE CONTROL REGISTER - OFFSET F0h ............................................................................. 66 MESSAGE ADDRESS REGISTER - OFFSET F4h .............................................................................. 66 MESSAGE UPPER ADDRESS REGISTER - OFFSET F8h................................................................. 66 MESSAGE DATA REGISTER - OFFSET FCh..................................................................................... 67 ADVANCE ERROR REPORTING CAPABILITY ID REGISTER - OFFSET 100h .............................. 67 ADVANCE ERROR REPORTING CAPABILITY VERSION REGISTER - OFFSET 100h .................. 67 NEXT CAPABILITY OFFSET REGISTER - OFFSET 100h ................................................................ 67 UNCORRECTABLE ERROR STATUS REGISTER - OFFSET 104h ................................................... 67 UNCORRECTABLE ERROR MASK REGISTER - OFFSET 108h ...................................................... 67 UNCORRECTABLE ERROR SEVERITY REGISTER - OFFSET 10Ch............................................... 68 CORRECTABLE ERROR STATUS REGISTER - OFFSET 110h......................................................... 68 CORRECTABLE ERROR MASK REGISTER - OFFSET 114h ............................................................ 68 ADVANCED ERROR CAPABILITIES AND CONTROL REGISTER - OFFSET 118h........................ 69 HEADER LOG REGISTER 1 - OFFSET 11Ch .................................................................................... 69 HEADER LOG REGISTER 2 - OFFSET 120h..................................................................................... 69 HEADER LOG REGISTER 3 - OFFSET 124h..................................................................................... 69 HEADER LOG REGISTER 4 - OFFSET 128h..................................................................................... 69 SECONDARY UNCORRECTABLE ERROR STATUS REGISTER - OFFSET 12Ch ........................... 69 SECONDARY UNCORRECTABLE ERROR MASK REGISTER - OFFSET 130h ............................... 70 SECONDARY UNCORRECTABLE ERROR SEVERITY REGISTER - OFFSET 134h ........................ 70 SECONDARY ERROR CAPABILITY AND CONTROL REGISTER - OFFSET 138h.......................... 71 SECONDARY HEADER LOG REGISTER - OFFSET 13Ch - 148h.................................................... 71 RESERVED REGISTER - OFFSET 14Ch ............................................................................................ 71 VC CAPABILITY ID REGISTER - OFFSET 150h ............................................................................... 71 VC CAPABILITY VERSION REGISTER - OFFSET 150h ................................................................... 71 NEXT CAPABILITY OFFSET REGISTER - OFFSET 150h ................................................................ 72 PORT VC CAPABILITY REGISTER 1 - OFFSET 154h ...................................................................... 72 PORT VC CAPABILITY REGISTER 2 - OFFSET 158h ...................................................................... 72 PORT VC CONTROL REGISTER - OFFSET 15Ch............................................................................. 72
Page 6 of 145 Pericom Semiconductor November 2007, Revision 2.4
PI7C9X110
PCIe-to-PCI Reversible Bridge
7.4.119 7.4.120 7.4.121 7.4.122 7.4.123 7.4.124 7.4.125 7.4.126 7.4.127
PORT VC STATUS REGISTER - OFFSET 15Ch................................................................................. 72 VC0 RESOURCE CAPABILITY REGISTER - OFFSET 160h ............................................................. 72 VC0 RESOURCE CONTROL REGISTER - OFFSET 164h ................................................................. 72 VC0 RESOURCE STATUS REGISTER - OFFSET 168h ..................................................................... 73 RESERVED REGISTERS - OFFSET 16Ch - 300h .............................................................................. 73 EXTRA GPI/GPO DATA AND CONTROL REGISTER - OFFSET 304h............................................. 73 RESERVED REGISTERS - OFFSET 308h - 30Ch .............................................................................. 73 REPLAY AND ACKNOWLEDGE LATENCY TIMERS - OFFSET 310h ............................................. 73 RESERVED REGISTERS - OFFSET 314h - FFCh ............................................................................. 73 VENDOR ID - OFFSET 00h ................................................................................................................ 74 DEVICE ID - OFFSET 00h.................................................................................................................. 74 COMMAND REGISTER - OFFSET 04h .............................................................................................. 74 PRIMARY STATUS REGISTER - OFFSET 04h................................................................................... 75 REVISION ID REGISTER - OFFSET 08h ........................................................................................... 76 CLASS CODE REGISTER - OFFSET 08h ........................................................................................... 76 CACHE LINE SIZE REGISTER - OFFSET 0Ch.................................................................................. 77 PRIMARY LATENCY TIMER REGISTER - OFFSET 0Ch .................................................................. 77 PRIMARY HEADER TYPE REGISTER - OFFSET 0Ch ...................................................................... 77 PRIMARY CSR AND MEMORY 0 BASE ADDRESS REGISTER - OFFSET 10h................................ 77 PRIMARY CSR I/O BASE ADDRESS REGISTER - OFFSET 14h ....................................................... 78 DOWNSTREAM I/O OR MEMORY 1 BASE ADDRESS REGISTER - OFFSET 18h .......................... 78 DONWSTREAM MEMORY 2 BASE ADDRESS REGISTER - OFFSET 1Ch ...................................... 79 DOWNSTREAM MEMORY 3 BASE ADDRESS REGISTER - OFFSET 20h....................................... 79 DOWNSTREAM MEMORY 3 UPPER BASE ADDRESS REGISTER - OFFSET 24h ......................... 80 RESERVED REGISTER - OFFSET 28h............................................................................................... 80 SUBSYTEM ID AND SUBSYSTEM VENDOR ID REGISTER - OFFSET 2Ch.................................... 80 RESERVED REGISTER - OFFSET 30h............................................................................................... 80 CAPABILITY POINTER - OFFSET 34h .............................................................................................. 80 EXPANSION ROM BASE ADDRESS REGISTER - OFFSET 38h ....................................................... 80 PRIMARY INTERRUPT LINE REGISTER - OFFSET 3Ch ................................................................. 80 PRIMARY INTERRUPT PIN REGISTER - OFFSET 3Ch.................................................................... 80 PRIMARY MINIMUM GRANT REGISTER - OFFSET 3Ch ................................................................ 81 PRIMARY MAXIMUM LATENCY TIME REGISTER - OFFSET 3Ch................................................. 82 PCI DATA BUFFERING CONTROL REGISTER - OFFSET 40h ....................................................... 82 CHIP CONTROL 0 REGISTER - OFFSET 40h................................................................................... 83 SECONDARY COMMAND REGISTER - OFFSET 44h ...................................................................... 84 SECONDARY STATUS REGISTER - OFFSET 44h............................................................................. 85 ARBITER ENABLE REGISTER - OFFSET 48h................................................................................... 87 ARBITER MODE REGISTER - OFFSET 48h...................................................................................... 87 ARBITER PRIORITY REGISTER - OFFSET 48h ................................................................................ 88 SECONDARY CACHE LINE SIZE REGISTER - OFFSET 4Ch .......................................................... 89 SECONDARY LATENCY TIME REGISTER - OFFSET 4Ch............................................................... 89 SECONDARY HEADER TYPE REGISTER - OFFSET 4Ch ................................................................ 89 SECONDARY CSR AND MEMORY 0 BASE ADDRESS REGISTER - OFFSET 50h.......................... 89 SECONDARY CSR I/O BASE ADDRESS REGISTER - OFFSET 54h ................................................. 90 UPSTREAM I/O OR MEMORY 1 BASE ADDRESS REGISTER - OFFSET 58h................................. 90 UPSTREAM MEMORY 2 BASE ADDRESS REGISTER - OFFSET 5Ch............................................. 91 UPSTREAM MEMORY 3 BASE ADDRESS REGISTER - OFFSET 60h ............................................. 91 UPSTREAM MEMORY 3 UPPER BASE ADDRESS REGISTER - OFFSET 64h................................ 93 EXPRESS TRANSMITTER/RECEIVER REGISTER - OFFSET 68h.................................................... 93 MEMORY ADDRESS FORWARDING CONTROL REGISTER - OFFSET 68h .................................. 94
7.5
PCI CONFIGURATION REGISTERS FOR NON-TRANSPARENT BRIDGE MODE..... 74
7.5.1 7.5.2 7.5.3 7.5.4 7.5.5 7.5.6 7.5.7 7.5.8 7.5.9 7.5.10 7.5.11 7.5.12 7.5.13 7.5.14 7.5.15 7.5.16 7.5.17 7.5.18 7.5.19 7.5.20 7.5.21 7.5.22 7.5.23 7.5.24 7.5.25 7.5.26 7.5.27 7.5.28 7.5.29 7.5.30 7.5.31 7.5.32 7.5.33 7.5.34 7.5.35 7.5.36 7.5.37 7.5.38 7.5.39 7.5.40 7.5.41 7.5.42
Page 7 of 145 Pericom Semiconductor November 2007, Revision 2.4
PI7C9X110
PCIe-to-PCI Reversible Bridge
7.5.43 7.5.44 7.5.45 7.5.46 7.5.47 7.5.48 7.5.49 7.5.50 7.5.51 7.5.52 7.5.53 7.5.54 7.5.55 7.5.56 7.5.57 7.5.58 7.5.59 7.5.60 7.5.61 7.5.62 7.5.63 7.5.64 7.5.65 7.5.66 7.5.67 7.5.68 7.5.69 7.5.70 7.5.71 7.5.72 7.5.73 7.5.74 7.5.75 7.5.76 7.5.77 7.5.78 7.5.79 7.5.80 7.5.81 7.5.82 7.5.83 7.5.84 7.5.85 7.5.86 7.5.87 7.5.88 7.5.89 7.5.90 7.5.91 7.5.92 7.5.93 7.5.94
UPSTREAM MEMORY WRITE FRAGMENT CONTROL REGISTER - OFFSET 68h ....................... 95 SUBSYSTEM VENDOR ID REGISTER - OFFSET 6Ch ...................................................................... 95 SUBSYSTEM ID REGISTER - OFFSET 6Ch....................................................................................... 95 EEPROM AUTOLOAD CONTROL/STATUS REGISTER - OFFSET 70h........................................... 95 RESERVED REGISTER - OFFSET 74h............................................................................................... 96 BRIDGE CONTROL AND STATUS REGISTER - OFFSET 78h ......................................................... 96 GPIO DATA AND CONTROL REGISTER - OFFSET 78h.................................................................. 97 SECONDARY INTERRUPT LINE REGISTER - OFFSET 7Ch ........................................................... 97 SECONDARY INTERRUPT PIN REGISTER - OFFSET 7Ch.............................................................. 97 SECONDARY MINIMUM GRANT REGISTER - OFFSET 7Ch .......................................................... 97 SECONDARY MAXIMUM LATENCY TIMER REGISTER - OFFSET 7Ch......................................... 98 PCI-X CAPABILITY ID REGISTER - OFFSET 80h ............................................................................ 98 NEXT CAPABILITY POINTER REGISTER - OFFSET 80h ................................................................ 98 PCI-X SECONDARY STATUS REGISTER - OFFSET 80h.................................................................. 98 PCI-X BRIDGE STATUS REGISTER - OFFSET 84h.......................................................................... 99 UPSTREAM SPLIT TRANSACTION REGISTER - OFFSET 88h ...................................................... 100 DOWNSTREAM SPLIT TRANSACTION REGISTER - OFFSET 8Ch ............................................... 100 POWER MANAGEMENT ID REGISTER - OFFSET 90h.................................................................. 100 NEXT CAPABILITY POINTER REGISTER - OFFSET 90h .............................................................. 101 POWER MANAGEMENT CAPABILITY REGISTER - OFFSET 90h ................................................ 101 POWER MANAGEMENT CONTROL AND STATUS REGISTER - OFFSET 94h ............................ 101 PCI-TO-PCI SUPPORT EXTENSION REGISTER - OFFSET 94h ................................................... 102 DOWNSTREAM MEMORY 0 TRANSLATED BASE REGISTER - OFFSET 98h .............................. 102 DOWNSTREAM MEMORY 0 SETUP REGISTER - OFFSET 9Ch ................................................... 102 CAPABILITY ID REGISTER - OFFSET A0h..................................................................................... 103 NEXT POINTER REGISTER - OFFSET A0h..................................................................................... 104 SLOT NUMBER REGISTER - OFFSET A0h ..................................................................................... 104 CHASSIS NUMBER REGISTER - OFFSET A0h ............................................................................... 104 SECONDARY CLOCK AND CLKRUN CONTROL REGISTER - OFFSET A4h............................... 104 DONWSTREAM I/O OR MEMORY 1 TRANSLATED BASE REGISTER - OFFSET A8h ................. 105 DOWSTREAM I/O OR MEMORY 1 SETUP REGISTER - OFFSET ACh ......................................... 106 PCI EXPRESS CAPABILITY ID REGISTER - OFFSET B0h ............................................................ 106 NEXT CAPABILITY POINTER REGISTER - OFFSET B0h .............................................................. 106 PCI EXPRESS CAPABILITY REGISTER - OFFSET B0h ................................................................. 106 DEVICE CAPABILITY REGISTER - OFFSET B4h........................................................................... 107 DEVICE CONTROL REGISTER - OFFSET B8h............................................................................... 108 DEVICE STATUS REGISTER - OFFSET B8h................................................................................... 108 LINK CAPABILITY REGISTER - OFFSET BCh ............................................................................... 109 LINK CONTROL REGISTER - OFFSET C0h.................................................................................... 109 LINK STATUS REGISTER - OFFSET C0h........................................................................................ 111 SLOT CAPABILITY REGISTER - OFFSET C4h ............................................................................... 111 SLOT CONTROL REGISTER - OFFSET C8h ................................................................................... 111 SLOT STATUS REGISTER - OFFSET C8h ....................................................................................... 112 XPIP CONFIGURATION REGISTER 0 - OFFSET CCh................................................................... 112 XPIP CONFIGURATION REGISTER 1 - OFFSET D0h ................................................................... 112 XPIP CONFIGURATION REGISTER 2 - OFFSET D4h ................................................................... 112 CAPABILITY ID REGISTER - OFFSET D8h .................................................................................... 113 NEXT POINTER REGISTER - OFFSET D8h .................................................................................... 113 VPD REGISTER - OFFSET D8h ....................................................................................................... 113 VPD DATA REGISTER - OFFSET DCh............................................................................................ 113 UPSTREAM MEMORY 0 TRANSLATED BASE REGISTER - OFFSET E0h .................................... 113 UPSTREAM MEMORY 0 SETUP REGISTER - OFFSET E4h .......................................................... 114
Page 8 of 145 Pericom Semiconductor November 2007, Revision 2.4
PI7C9X110
PCIe-to-PCI Reversible Bridge
7.5.95 7.5.96 7.5.97 7.5.98 7.5.99 7.5.100 7.5.101 7.5.102 7.5.103 7.5.104 7.5.105 7.5.106 7.5.107 7.5.108 7.5.109 7.5.110 7.5.111 7.5.112 7.5.113 7.5.114 7.5.115 7.5.116 7.5.117 7.5.118 7.5.119 7.5.120 7.5.121 7.5.122 7.5.123 7.5.124 7.5.125 7.5.126 7.5.127 7.5.128 7.5.129 7.5.130 7.5.131 7.5.132 7.5.133 7.5.134 7.5.135 7.5.136
UPSTREAM I/O OR MEMORY 1 TRANSLATED BASE REGISTER - OFFSET E8h ....................... 114 UPSTREAM I/O OR MEMORY 1 SETUP REGISTER - OFFSET ECh............................................. 114 MESSAGE SIGNALED INTERRUPTS ID REGISTER - F0h............................................................. 116 NEXT CAPABILITIES POINTER REGISTER - F0h.......................................................................... 116 MESSAGE CONTROL REGISTER - OFFSET F0h ........................................................................... 116 MESSAGE ADDRESS REGISTER - OFFSET F4h ............................................................................ 116 MESSAGE UPPER ADDRESS REGISTER - OFFSET F8h............................................................... 116 MESSAGE DATA REGISTER - OFFSET FCh................................................................................... 116 ADVANCE ERROR REPORTING CAPABILITY ID REGISTER - OFFSET 100h ............................ 117 ADVANCE ERROR REPORTING CAPABILITY VERSION REGISTER - OFFSET 100h ................ 117 NEXT CAPABILITY OFFSET REGISTER - OFFSET 100h .............................................................. 117 UNCORRECTABLE ERROR STATUS REGISTER - OFFSET 104h ................................................. 117 UNCORRECTABLE ERROR MASK REGISTER - OFFSET 108h .................................................... 117 UNCORRECTABLE ERROR SEVERITY REGISTER - OFFSET 10Ch............................................. 118 CORRECTABLE ERROR STATUS REGISTER - OFFSET 110h....................................................... 118 CORRECTABLE ERROR MASK REGISTER - OFFSET 114h .......................................................... 118 ADVANCED ERROR CAPABILITIES AND CONTROL REGISTER - OFFSET 118h...................... 119 HEADER LOG REGISTER 1 - OFFSET 11Ch .................................................................................. 119 HEADER LOG REGISTER 2 - OFFSET 120h................................................................................... 119 HEADER LOG REGISTER 3 - OFFSET 124h................................................................................... 119 HEADER LOG REGISTER 4 - OFFSET 128h................................................................................... 119 SECONDARY UNCORRECTABLE ERROR STATUS REGISTER - OFFSET 12Ch ......................... 119 SECONDARY UNCORRECTABLE ERROR MASK REGISTER - OFFSET 130h ............................. 120 SECONDARY UNCORRECTABLE ERROR SEVERITY REGISTER - OFFSET 134h ...................... 120 SECONDARY ERROR CAPABILITY AND CONTROL REGISTER - OFFSET 138h........................ 121 SECONDARY HEADER LOG REGISTER - OFFSET 13Ch - 148h.................................................. 121 RESERVED REGISTER - OFFSET 14Ch .......................................................................................... 121 VC CAPABILITY ID REGISTER - OFFSET 150h ............................................................................. 121 VC CAPABILITY VERSION REGISTER - OFFSET 150h ................................................................. 121 NEXT CAPABILITY OFFSET REGISTER - OFFSET 150h .............................................................. 122 PORT VC CAPABILITY REGISTER 1 - OFFSET 154h .................................................................... 122 PORT VC CAPABILITY REGISTER 2 - OFFSET 158h .................................................................... 122 PORT VC CONTROL REGISTER - OFFSET 15Ch........................................................................... 122 PORT VC STATUS REGISTER - OFFSET 15Ch............................................................................... 122 VC0 RESOURCE CAPABILITY REGISTER - OFFSET 160h ........................................................... 122 VC0 RESOURCE CONTROL REGISTER - OFFSET 164h ............................................................... 122 VC0 RESOURCE STATUS REGISTER - OFFSET 168h ................................................................... 123 RESERVED REGISTERS - OFFSET 16Ch - 300h ............................................................................ 123 EXTRA GPI/GPO DATA AND CONTROL REGISTER - OFFSET 304h........................................... 123 RESERVED REGISTERS - OFFSET 308h - 30Ch ............................................................................ 123 REPLAY AND ACKNOWLEDGE LATENCY TIMERS - OFFSET 310h ........................................... 123 RESERVED REGISTERS - OFFSET 314h - FFCh ........................................................................... 123
7.6
7.6.1 7.6.2 7.6.3 7.6.4 7.6.5 7.6.6 7.6.7 7.6.8
CONTROL AND STATUS REGISTERS FOR NON-TRANSPARENT BRIDGE MODE 124
RESERVED REGISTERS - OFFSET 000h TO 004h.......................................................................... 124 DOWNSTREAM MEMORY 2 TRANSLATED BASE REGISTER - OFFSET 008h ............................ 124 DOWNSTREAM MEMORY 2 SETUP REGISTER - OFFSET 00Ch.................................................. 124 DOWNSTREAM MEMORY 3 TRANSLATED BASE REGISTER - OFFSET 010h ............................ 124 DOWNSTREAM MEMORY 3 SETUP REGISTER - OFFSET 014h .................................................. 125 DOWNSTREAM MEMORY 3 UPPER 32-BIT SETUP REGISTER - OFFSET 018h ........................ 125 RESERVED REGISTERS - OFFSET 01Ch TO 030h ......................................................................... 125 UPSTREAM MEMORY 3 SETUP REGISTER - OFFSET 34h........................................................... 125
Page 9 of 145 Pericom Semiconductor November 2007, Revision 2.4
PI7C9X110
PCIe-to-PCI Reversible Bridge
7.6.9 7.6.10 7.6.11 7.6.12 7.6.13 7.6.14 7.6.15 7.6.16 7.6.17 7.6.18 7.6.19 7.6.20 7.6.21 7.6.22 7.6.23 7.6.24 7.6.25 7.6.26 7.6.27 7.6.28 7.6.29 7.6.30 7.6.31 7.6.32 7.6.33 7.6.34 7.6.35 7.6.36 7.6.37
UPSTREAM MEMORY 3 UPPER 32-BIT SETUP REGISTER - OFFSET 038h............................... 126 RESERVED REGISTERS - OFFSET 03Ch TO 04Ch ........................................................................ 126 LOOKUP TABLE OFFSET - OFFSET 050h ..................................................................................... 126 LOOKUP TABLE DATA - OFFSET 054h.......................................................................................... 126 UPSTREAM PAGE BOUNDARY IRQ 0 REQUEST REGISTER - OFFSET 058h ............................ 127 UPSTREAM PAGE BOUNDARY IRQ 1 REQUEST REGISTER - OFFSET 05Ch............................ 127 UPSTREAM PAGE BOUNDARY IRQ 0 MASK REGISTER - OFFSET 060h ................................... 128 UPSTREAM PAGE BOUNDARY IRQ 1 MASK REGISTER - OFFSET 064h ................................... 128 RESERVED REGISTER - OFFSET 068C .......................................................................................... 128 PRIMARY CLEAR IRQ REGISTER - OFFSET 070h......................................................................... 128 SECONDARY CLEAR IRQ REGISTER - OFFSET 070h................................................................... 128 PRIMARY SET IRQ REGISTER - OFFSET 074h .............................................................................. 129 SECONDARY SET IRQ REGISTER - OFFSET 074h ........................................................................ 129 PRIMARY CLEAR IRQ MASK REGISTER - OFFSET 078h ............................................................. 129 SECONDARY CLEAR IRQ MASK REGISTER - OFFSET 078h ....................................................... 129 PRIMARY SET IRQ MASK REGISTER - OFFSET 07Ch .................................................................. 130 SECONDARY SET IRQ MASK REGISTER - OFFSET 07Ch ............................................................ 130 RESERVED REGISTERS - OFFSET 080h TO 09Ch ......................................................................... 130 SCRATCHPAD 0 REGISTER - OFFSET 0A0h.................................................................................. 130 SCRATCHPAD 1 REGISTER - OFFSET 0A4h.................................................................................. 130 SCRATCHPAD 2 REGISTER - OFFSET 0A8h.................................................................................. 131 SCRATCHPAD 3 REGISTER - OFFSET 0ACh ................................................................................. 131 SCRATCHPAD 4 REGISTER - OFFSET 0B0h.................................................................................. 131 SCRATCHPAD 5 REGISTER - OFFSET 0B4h.................................................................................. 131 SCRATCHPAD 6 REGISTER - OFFSET 0B8h.................................................................................. 131 SCRATCHPAD 7 REGISTER - OFFSET 0BCh ................................................................................. 132 RESERVED REGISTERS - OFFSET 0C0h TO 0FCh........................................................................ 132 LOOKUP TABLE REGISTERS - OFFSET 100h TO 1FCh ............................................................... 132 RESERVED REGISTERS - OFFSET 200h TO FFCh ........................................................................ 132
8 9 10 11
GPIO PINS AND SM BUS ADDRESS..................................................................................... 133 CLOCK SCHEME ..................................................................................................................... 133 INTERRUPTS......................................................................................................................... 133 EEPROM (I2C) INTERFACE AND SYSTEM MANAGEMENT BUS ........................... 134
11.1 11.2 EEPROM (I2C) INTERFACE .......................................................................................................................... 134 SYSTEM MANAGEMENT BUS..................................................................................................................... 134
12 13 14
14.1 14.2 14.3 14.4 14.5
HOT PLUG OPERATION .................................................................................................... 134 RESET SCHEME................................................................................................................... 135 IEEE 1149.1 COMPATIBLE JTAG CONTROLLER ....................................................... 136
INSTRUCTION REGISTER ............................................................................................................................ 136 BYPASS REGISTER........................................................................................................................................ 136 DEVICE ID REGISTER................................................................................................................................... 136 BOUNDARY SCAN REGISTER..................................................................................................................... 137 JTAG BOUNDARY SCAN REGISTER ORDER............................................................................................ 137
15 16
POWER MANAGEMENT .................................................................................................... 140 ELECTRICAL AND TIMING SPECIFICATIONS........................................................... 141
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PI7C9X110
PCIe-to-PCI Reversible Bridge
16.1 16.2 16.3
ABSOLUTE MAXIMUM RATINGS .............................................................................................................. 141 DC SPECIFICATIONS..................................................................................................................................... 141 AC SPECIFICATIONS..................................................................................................................................... 142
17 18
PACKAGE INFORMATION................................................................................................ 143 ORDERING INFORMATION.............................................................................................. 144
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PI7C9X110
PCIe-to-PCI Reversible Bridge
TABLE OF FIGURES
FIGURE 1-1 PI7C9X110 TOPOLOGY ...................................................................................................................................... 14 FIGURE 3-1 PCI / PCI-X SELECTION ...................................................................................................................................... 21 FIGURE 4-1 FORWARD AND NON-TRANSPARENT BRIDGE MODE ............................................................................................ 22 FIGURE 4-2 REVERSE AND TRANSPARENT BRIDGE MODE ...................................................................................................... 23 FIGURE 16-1 PCI SIGNAL TIMING CONDITIONS ..................................................................................................................... 142 FIGURE 17-1 TOP VIEW DRAWING ......................................................................................................................................... 143 FIGURE 17-2 BOTTOM VIEW DRAWING.................................................................................................................................. 143 FIGURE 17-3 PACKAGE OUTLINE DRAWING........................................................................................................................... 144
LIST OF TABLES
TABLE 2-1 PIN ASSIGNMENTS................................................................................................................................................. 19 TABLE 3-1 MODE SELECTION ................................................................................................................................................. 20 TABLE 3-2 PIN STRAPPING...................................................................................................................................................... 21 TABLE 5-1 NON-TRANSPARENT REGISTERS ............................................................................................................................ 25 TABLE 6-1 TLP FORMAT ........................................................................................................................................................ 26 TABLE 7-1 CONFIGURATION REGISTER MAP (00H - FFH) ...................................................................................................... 27 TABLE 7-2 PCI EXPRESS EXTENDED CAPABILITY REGISTER MAP (100H - FFFH) ................................................................. 30 TABLE 7-3 CONTROL AND STATUS REGISTER (CSR) MAP (000H - FFFH) ............................................................................. 31 TABLE 8-1 SM BUS DEVICE ID STRAPPING.......................................................................................................................... 133 TABLE 10-1 PCIE INTERRUPT MESSAGE TO PCI INTERRUPT MAPPING IN REVERSE BRIDGE MODE......................................... 134 TABLE 10-2 PCI INTERRUPT TO PCIE INTERRUPT MESSAGE MAPPING IN FORWARD BRIDGE MODE ....................................... 134 TABLE 14-1 INSTRUCTION REGISTER CODES ......................................................................................................................... 136 TABLE 14-2 JTAG DEVICE ID REGISTER .............................................................................................................................. 137 TABLE 14-3 JTAG BOUNDARY SCAR REGISTER DEFINITION ................................................................................................. 137 TABLE 16-1 ABSOLUTE MAXIMUM RATINGS ......................................................................................................................... 141 TABLE 16-2 DC ELECTRICAL CHARACTERISTICS .................................................................................................................. 141 TABLE 16-3 PCI BUS TIMING PARAMETERS .......................................................................................................................... 142
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PI7C9X110
PCIe-to-PCI Reversible Bridge
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PI7C9X110
PCIe-to-PCI Reversible Bridge
1
INTRODUCTION
PI7C9X110 is a PCIe-to-PCI/PCI-X bridge. PI7C9X110 is compliant with the PCI Express Base Specification, Revision 1.0a, the PCI Express Card Electromechanical Specification, Revision 1.0a, the PCI Local Bus Specification, Revision 3.0 and PCI Express to PCI/PCI-X Bridge Specification, Revision 1.0. PI7C9X110 supports transparent and non-transparent mode of operations. Also, PI7C9X110B supports forward and reverse bridging. In forward bridge mode, PI7C9X110 has an x1 PCI Express upstream port and a 32-bit PCI/PCI-X downstream port. The 32-bit PCI downstream port is 66MHz capable (see figure 1-1). In reverse bridge mode, PI7C9X110 has a 32-bit PCI upstream port and an x1 PCI Express downstream port. PI7C9X110 configuration registers are backward compatible with existing PCI bridge software and firmware. No modification of PCI bridge software and firmware is needed for the original operation. Figure 1-1 PI7C9X110 Topology Tx Rx
x1 PCI Express Port
PI7C9X110
PCI 32bit / 66MHz Bus
PCI Device
PCI Device
PCI Device
PCI Device
PCI Device
PCI Device
PCI Device
PCI Device
1.1
PCI EXPRESS FEATURES
* * * * * * * * * * * Compliant with PCI Express Base Specification, Revision 1.0a Compliant with PCI Express Card Electromechanical Specification, Revision 1.0a Compliant with PCI Express to PCI/PCI-X Bridge Specification, Revision 1.0 Physical Layer interface (x1 link with 2.5Gb/s data rate) Lane polarity toggle Virtual Isochronous support (upstream TC1-7 generation, downstream TC1-7 mapping) ASPM support Beacon support CRC (16-bit), LCRC (32-bit) ECRC and advanced error reporting PRBS (Pseudo Random Bit Sequencing) generator/checker for chip testing
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PI7C9X110
PCIe-to-PCI Reversible Bridge
*
Maximum payload size to 512 bytes
1.2
PCI / PCI-X FEATURES
* * * * * * * * * * * * Compliant with PCI Local Bus Specification, Revision 3.0 Compliant with PCI-to-PCI Bridge Architecture Specification, Revision 1.2 Compliant with PCI Bus PM Interface Specification, Revision 1.1 Compliant with PCI Hot-Plug Specification, Revision 1.1 Compliant with PCI Mobile Design Guide, Version 1.1 Compliant with PCI-X Protocol Addendum to the PCI Local Bus Specification, Revision 2.0a PME support 3.3V PCI signaling with 5V I/O tolerance Provides two level arbitration support for eight PCI Bus masters 16-bit address decode for VGA Subsystem Vendor and Subsystem Device IDs support PCI INT interrupt or MSI Function support
1.3
GENERAL FEATURES
* * * * * * * * * * * * * * Compliant with Advanced Configuration and Power Interface Specification (ACPI), Revision 2.0b Compliant with System Management (SM) Bus, Version 2.0 Forward bridging (PCI Express as primary bus, PCI as secondary bus) Reverse bridging (PCI as primary bus, PCI Express as secondary bus) Transparent mode support Non-transparent mode Support GPIO support (4 bi-directional pins) Power Management (including ACPI, CLKRUN_L, PCI_PM) Masquerade Mode (pre-loadable vendor, device, and revision IDs) EEPROM (I2C) Interface SM Bus Interface Auxiliary powers (VAUX, VDDAUX, VDDCAUX) support Power consumption at about 1.0 Watt in typical condition Extended commercial temperature range (0C to 85C)
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PI7C9X110
PCIe-to-PCI Reversible Bridge
2
2.1
PIN DEFINITIONS
SIGNAL TYPES
TYPE OF SIGNAL - DESCRIPTIONS B I IU ID IOD OD O P G Bi-directional Input Input with pull-up Input with pull-down Bi-directional with open drain output Open drain output Output Power Ground
2.2
PCI EXPRESS SIGNALS
NAME REFCLKP REFCLKN RP RN TP TN RREF PERST_L PIN ASSIGNMENT E3, E2 G4, H4 G1, F1 H3 L3 TYPE I I O I I DESCRIPTION Reference Clock Inputs: Connect to external 100MHz differential clock. PCI Express data inputs: Differential data receiver input signals PCI Express data outputs: Differential data transmitter output signals Resistor Reference: It is used to connect an external resistor (2.4K Ohm +/- 1%) to VSS to provide a reference current for the driver and equalization circuit. PCI Express Fundamental Reset: PI7C9X110B uses this reset to initialize the internal state machines.
2.3 PCI SIGNALS
NAME AD [31:0] PIN ASSIGNMENT B3, A4, B4, D4, A5, C5, D5, B6, A7, B7, D7, A8, C8, D8, B9, C9, C12, D14, D12, D11, E13, F14, F13, F11, G12, G11, H13, H12, J14, J13, J11, K14 C6, A10, C14, G14 TYPE B DESCRIPTION Address / Data: Multiplexed address and data bus. Address phase is aligned with first clock of FRAME_L assertion. Data phase is aligned with IRDY_L or TRDY_L assertion. Data is transferred on rising edges of FBCLKIN when both IRDY_L and TRDY_L are asserted. During bus idle (both FRAME_L and IRDY_L are deasserted), PI7C9X110B drives AD to a valid logic level when arbiter is parking to PI7C9X110B on PCI bus.
CBE [3:0]
B
PAR
B13
B
FRAME_L
B10
B
Command / Byte Enables (Active LOW): Multiplexed command at address phase and byte enable at data phase. During address phase, the initiator drives commands on CBE [3:0] signals to start the transaction. If the command is a write transaction, the initiator will drive the byte enables during data phase. Otherwise, the target will drive the byte enables during data phase. During bus idle, PI7C9X110B drives CBE [3:0] signals to a valid logic level when arbiter is parking to PI7C9X110B on PCI bus. Parity Bit: Parity bit is an even parity (i.e. even number of 1's), which generates based on the values of AD [31:0], CBE [3:0]. If PI7C9X110B is an initiator with a write transaction, PI7C9X110B will tri-state PAR. If PI7C9X110B is a target and a write transaction, PI7C9X110B will drive PAR one clock after the address or data phase. If PI7C9X110B is a target and a read transaction, PI7C9X110B will drive PAR one clock after the address phase and tri-state PAR during data phases. PAR is tri-stated one cycle after the AD lines are tri-stated. During bus idle, PI7C9X110B drives PAR to a valid logic level when arbiter is parking to PI7C9X110B on PCI bus. FRAME (Active LOW): Driven by the initiator of a transaction to indicate the beginning and duration an access. The de-assertion of FRAME_L indicates the final data phase signaled by the initiator in burst transfers. Before being tri-stated, it is driven to a de-asserted state for one cycle.
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PI7C9X110
PCIe-to-PCI Reversible Bridge
NAME IRDY_L
PIN ASSIGNMENT D10
TYPE B
TRDY_L
A11
B
DEVSEL_L
B11
B
STOP_L
A12
B
LOCK_L IDSEL PERR_L
A13 N14 A14
B I B
SERR_L
B14
IOD
REQ_L [7:0]
P2, P1, N3, N2, N1, M3, M2, M1
I
GNT_L [7:0]
N6, P6, P5, N5, M5, L5, N4, M4
O
CLKOUT [8:0] RESET_L INTA_L INTB_L INTC_L INTD_L FBCLKIN CLKIN
N12, P12, N11, L10, M10, P10, L9, N9, P9 N7 P3 M6 P13 N13 C2 P7
O B IOD
I I
DESCRIPTION IRDY (Active LOW): Driven by the initiator of a transaction to indicate its ability to complete current data phase on the primary side. Once asserted in a data phase, it is not de-asserted until the end of the data phase. Before tri-stated, it is driven to a deasserted state for one cycle. TRDY (Active LOW): Driven by the target of a transaction to indicate its ability to complete current data phase on the primary side. Once asserted in a data phase, it is not de-asserted until the end of the data phase. Before tri-stated, it is driven to a deasserted state for one cycle. Device Select (Active LOW): Asserted by the target indicating that the device is accepting the transaction. As a master, PI7C9X110 waits for the assertion of this signal within 5 cycles of FRAME_L assertion; otherwise, terminate with master abort. Before tri-stated, it is driven to a de-asserted state for one cycle. STOP (Active LOW): Asserted by the target indicating that the target is requesting the initiator to stop the current transaction. Before tri-stated, it is driven to a deasserted state for one cycle. LOCK (Active LOW): Asserted by the initiator for multiple transactions to complete. PI7C9X110B does not support any upstream LOCK transaction. Initialization Device Select: Used as a chip select line for Type 0 configuration access to bridge's configuration space. Parity Error (Active LOW): Asserted when a data parity error is detected for data received on the PCI bus interface. Before being tri-stated, it is driven to a de-asserted state for one cycle. System Error (Active LOW): Can be driven LOW by any device to indicate a system error condition. If SERR control is enabled, PI7C9X110B will drive this pin on: Address parity error Posted write data parity error on target bus Master abort during posted write transaction Target abort during posted write transaction Posted write transaction discarded Delayed write request discarded Delayed read request discarded Delayed transaction master timeout Errors reported from PCI Express port (advanced error reporting) in transparent mode. This signal is an open drain buffer that requires an external pull-up resistor for proper operation. Request (Active LOW): REQ_L's are asserted by bus master devices to request for transactions on the PCI bus. The master devices de-assert REQ_Ls for at least 2 PCI clock cycles before asserting them again. If external arbiter is selected (CFN_L=1), REQ_L [0] will be the bus grant input to PI7C9X110. Also, REQ_L [5:2] will become the GPI [3:0]. Grant (Active LOW): PI7C9X110 asserts GNT_Ls to release PCI bus control to bus master devices. During idle and all GNT_Ls are de-asserted and arbiter is parking to PI7C9X110, PI7C9X110 will drive AD, CBE, and PAR to valid logic levels. If external arbiter is selected (CFN_L=1), GNT_L [0] will be the bus request from PI7C9X110 to external arbiter. Also, GNT_L [5:2] will become the GPO [3:0]. PCI Clock Outputs: PCI clock outputs are derived from the CLKIN and provide clocking signals to external PCI Devices. RESET_L (Active LOW): When RESET_L active, all PCI signals should be asynchronously tri-stated. Interrupt: Signals are asserted to request an interrupt. After asserted, it can be cleared by the device driver. INTA_L, INTB_L, INTC_L, INTD_L signals are inputs and asynchronous to the clock in the forward mode. In reverse mode, INTA_L, INTB_L, INTC_L, and INTD_L are open drain buffers for sending interrupts to the host interrupt controller. Feedback Clock Input: It connects to one of the CLKOUT [8:0] Output Signals and provides internal clocking to PI7C9X110 PCI bus interface. PCI Clock Input: PCI Clock Input Signal connects to an external clock source. The PCI Clock Outputs CLKOUT [8:0] pins are derived from CLKIN Input.
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PI7C9X110
PCIe-to-PCI Reversible Bridge
2.4
MODE SELECT AND STRAPPING SIGNALS
NAME TM2 PIN ASSIGNMENT K3 TYPE I DESCRIPTION Mode Select 2: TM2 is a strapping pin. When TM2 is strapped low for normal operations and strapped high for testing functions. See table 3-1 for mode selection and 3-2 for strapping control for details. Mode Select 1: Mode Selection Pin to select EEPROM or SM Bus. TM1=0 for EEPROM (I2C) support and TM1=1 for SM Bus support. TM1 is also a strapping pin. See table 3-1 mode selection and 3-2 for strapping control. Mode Select 0: Mode Selection Pin to select transparent or non-transparent mode. TM0=0 for transparent bridge function mode and TM0=1 for non-transparent bridge function mode. TM0 is also a strapping pin. See table 3-1 for mode selection and 3-2 for strapping control. Mask Input for CLKOUT: MSK_IN is used by PI7C9X110 to enable or disable the clock outputs. MSK_IN is also a strapping pin. When it is strapped to high, hot-plug is enabled. See table 3-2 for strapping control. Forward or Reverse Bridging Pin: REVRSB pin controls the Forward (REVRSB=0) or Reverse (REVRSB=1) Bridge Mode of PI7C9X110. This pin is also a strapping pin. See table 3-1 for mode selection. Bus Central Function Control Pin (Active Low): To enable the internal arbiter, CFN_L pin should be tied low. When it's tied high, an external arbiter is required to arbitrate the bus. In external arbiter mode, REQ_L [0] is re-configured to be the secondary bus grant input, and GNT_L [0] is reconfigured to be the secondary bus request output. Also, REQ_L [5:2] and GNT_L [5:2] become GPI [3:0] and GPO [3:0] respectively if external arbiter is selected. CFN_L has a weak internal pull-down resistor. See table 3-1 for mode selection.
TM1
C1
I
TM0
D1
I
MSK_IN
P14
I
REVRSB
M12
I
CFN_L
M7
ID
2.5
JTAG BOUNDARY SCAN SIGNALS
NAME TCK TMS TDO TDI PIN ASSIGNMENT L14 L13 M13 M14 TYPE IU IU O IU DESCRIPTION Test Clock: TCK is the test clock to synchronize the state information and data on the PCI bus side of PI7C9X110 during boundary scan operation. Test Mode Select: TMS controls the state of the Test Access Port (TAP) controller. Test Data Output: TDO is the test data output and connects to the end of the JTAG scan chain. Test Data Input: TDI is the test data input and connects to the beginning of the JTAG scan chain. It allows the test instructions and data to be serially shifted into the PCI side of PI7C9X110. Test Reset (Active LOW): TRST_L is the test reset to initialize the Test Access Port (TAP) controller.
TRST_L
K11
IU
2.6
MISCELLANEOUS SIGNALS
NAME GPIO [3:0] PIN ASSIGNMENT L7, P8, M8, L8 TYPE B DESCRIPTION General Purpose I/O Data Pins: The 4 general-purpose signals are programmable as either input-only or bi-directional signals by writing the GPIO output enable control register in the configuration space. See Chapter 8 for more information. SMBUS / EEPROM Clock Pin: When EEPROM (I2C) interface is selected (TM1=0), this pin is an output of SCL clock and connected to EEPROM clock input. When SMBUS interface is selected (TM1=1), this pin is an input for the clock of SMBUS. SMBUS / EEPROM Data Pin: Data Interface Pin to EERPOM or SMBUS. When EEPROM (I2C) interface is selected (TM1=0), this pin is a bi-directional signal. When SMBUS interface is selected (TM1=1), this pin is an open drain signal. Power Management Event Pin: Power Management Event Signal is asserted to request a change in the device or link power state. Clock Run Pin (Active LOW): The Clock Run signal, for mobile environment, is asserted and de-asserted to indicate the status of the PCI Clock.
SMBCLK / SCL
A2
B
SMBDATA / SDA PME_L CLKRUN_L
A1
B/IOD
A3 D3
B B
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PI7C9X110
PCIe-to-PCI Reversible Bridge
NAME PCIXCAP
PIN ASSIGNMENT B1
TYPE I
PCIXUP
D2
O
DESCRIPTION PCI-X Capability Pin: PI7C9X110 can be forced to PCI mode if PCIXCAP is tied to ground with a capacitor (0.1uF) in parallel. If PCIXCAP is connected to ground through a capacitor (0.1uF), PI7C9X110 will be in 133MHz PCI-X mode. If PCIXCAP is connected to ground through a resistor (10K Ohm) with a capacitor (0.1uF) in parallel, PI7C9X110 will be in 66MHz PCI-X mode. PCIXCAP Pull-up driver: PI7C9X110 drives this pin for PCI-X mode detection.
2.7
POWER AND GROUND PINS
NAME VDDA VDDP VDDAUX VTT VDDA_PLL VDDC VDDCAUX VD33 PIN ASSIGNMENT J3, G3 F3, F4, K2 F2 G2, K1 J4 L1, N8, L11, L12, B12, C10, E4 L2 L4, N10, M11, K12, J12, H14, F12, E11, D13, A9, C7, A6, C4 B2 E1, H1, H2, J2, J1, K4, P4, L6, M9, P11, K13, H11, G13, E12, E14, C13, C11, D9, B8, D6, B5, C3 J3, G3 TYPE P P P P P P P P DESCRIPTION Analog Voltage Supply for PCI Express Interface: Connect to the 1.8V Power Supply. Digital Voltage Supply for PCI Express Interface: Connect to the 1.8V Power Supply. Auxiliary Voltage Supply for PCI Express Interface: Connect to the 1.8V Power Supply. Termination Supply Voltage for PCI Express Interface: Connect to the 1.8V Power Supply. Analog Voltage Supply for PLL at PCI Interface: Connect to the 1.8V Power Supply. Core Supply Voltage: Connect to the 1.8V Power Supply. Auxiliary Core Supply Voltage: Connect to the 1.8V Power Supply. I/O Supply Voltage for PCI Interface: Connect to the 3.3V Power Supply for PCI I/O Buffers. Auxiliary I/O Supply Voltage for PCI interface: Connect to the 3.3V Power Supply. Ground: Connect to Ground.
VAUX VSS
P P
VDDA
P
Analog Voltage Supply for PCI Express Interface: Connect to the 1.8V Power Supply.
2.8
PIN ASSIGNMENTS
Table 2-1 Pin Assignments
PIN A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 B1 B2 B3 B4 B5 NAME SMBDAT / SDA SMBCLK / SCL PME_L AD [30] AD [27] VD33 AD [23] AD [20] VD33 CBE [2] TRDY_L STOP_L LOCK_L PERR_L PCIXCAP VAUX AD [31] AD [29] VSS PIN C13 C14 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 E1 E2 E3 NAME VSS CBE [1] TM0 PCIXUP CLKRUN_L AD [28] AD [25] VSS AD [21] AD [18] VSS IRDY_L AD [12] AD [13] VD33 AD [14] VSS REFCLKN REFCLKP PIN H1 H2 H3 H4 H11 H12 H13 H14 J1 J2 J3 J4 J11 J12 J13 J14 K1 K2 K3 NAME VSS VSS RREF RN VSS AD [4] AD [5] VD33 VSS VSS VDDA VDDA_PLL AD [1] VD33 AD [2] AD [3] VTT VDDP TM2 PIN M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 N1 N2 N3 N4 N5 N6 N7 NAME REQ_L[2]/GPI[0] GNT_L [0] GNT_L[3]/GPO[1] INTB_L CFN_L GPIO [1] VSS CLKOUT [4] VD33 REVRSB TDO TDI REQ_L[3] / GPI[1] REQ_L[4] / GPI[2] REQ_L[5] / GPI[3] GNT_L [1] GNT_L[4]/GPO[2] GNT_L [7] RESET_L
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PI7C9X110
PCIe-to-PCI Reversible Bridge
PIN B6 B7 B8 B9 B10 B11 B12 B13 B14 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12
NAME AD [24] AD [22] VSS AD [17] FRAME_L DEVSEL_L VDDC PAR SERR_L TM1 FBCLKIN VSS VD33 AD [26] CBE [3] VD33 AD [19] AD [16] VDDC VSS AD [15]
PIN E4 E11 E12 E13 E14 F1 F2 F3 F4 F11 F12 F13 F14 G1 G2 G3 G4 G11 G12 G13 G14
NAME VDDC VD33 VSS AD [11] VSS TN VDDAUX VDDP VDDP AD [8] VD33 AD [9] AD [10] TP VTT VDDA RP AD [6] AD [7] VSS CBE [0]
PIN K4 K11 K12 K13 K14 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 M1 M2
NAME VSS TRST_L VD33 VSS AD [0] VDDC VDDCAUX PERST_L VD33 GNT_L[2]/GPO[0] VSS GPIO [3] GPIO [0] CLKOUT [2] CLKOUT [5] VDDC VDDC TMS TCK REQ_L [0] REQ_L [1]
PIN N8 N9 N10 N11 N12 N13 N14 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14
NAME VDDC CLKOUT [1] VD33 CLKOUT [6] CLKOUT [8] INTD_L IDSEL REQ_L [6] REQ_L [7] INTA_L VSS GNT_L[5]/GPO[3] GNT_L [6] CLKIN GPIO [2] CLKOUT [0] CLKOUT [3] VSS CLKKOUT [7] INTC_L MSK_IN
3
3.1
MODE SELECTION AND PIN STRAPPING
FUNCTIONAL MODE SELECTION
If TM2 is strapped to low, PI7C9X110 uses TM1, TM0, CFN_L, and REVRSB pins to select different modes of operations. These four input signals are required to be stable during normal operation. One of the sixteen combinations of normal operation can be selected by setting the logic values for the four mode select pins. For example, if the logic values are low for all four (TM1, TM0, CFN_L, and REVRSB) pins, the normal operation will have EEPROM (I2C) support in transparent mode with internal arbiter in forward bridge mode. The designated operation with respect to the values of the TM1, TM0, CFN_L, and REVRSB pins are defined on Table 3-1: Table 3-1 Mode Selection
TM2 Strapped 0 0 0 0 0 0 0 0 TM1 0 1 X X X X X X TM0 X X 0 1 X X X X CFN_L X X X X 0 1 X X REVRSB X X X X X X 0 1 Functional Mode EEPROM (I2C) support SM Bus support Transparent mode Non-Transparent mode Internal arbiter External arbiter Forward bridge mode Reverse bridge mode
3.2
PCI / PCI-X SELECTION
The secondary interface is capable of operating in either conventional PCI mode or in PCI-X mode. PI7C9X110 controls the mode and frequency for the secondary bus by utilizing a pull-up circuit connected to PCIXCAP. There are two pull-up resistors in the circuit as recommended by the PCI-X addendum. The first resistor is a weak pull-up (56K ohms) whose value is selected to set the voltage of PCIXCAP below its low threshold when a PCI-X 66MHz device is attached to the secondary bus. The second resistor is a strong pull-up, externally wired between PCIXCAP and PCIXUP. The value of the resistor (1K ohm) is selected to set the voltage of PCIXCAP above its high threshold when all devices on the secondary are PCI-X 66MHz capable. To detect the mode and frequency of the secondary bus, PCIXUP is initially disabled and PI7C9X110 samples the value on PCIXCAP.
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PI7C9X110
PCIe-to-PCI Reversible Bridge
If PI7C9X110 sees a logic LOW on PCIXCAP, one or more devices on the secondary have either pulled the signal to ground (PCI-X 66MHz capable) or tied it to ground (only capable of conventional PCI mode). To differentiate between the two conditions, PI7C9X110 then enables PCIXUP to put the strong pull-up into the circuit node. If PCIXCAP remains at logic LOW, it must be tied to ground by one or more devices, and the bus is initialized to conventional PCI mode. If PCIXUP can be pulled up, one or more devices are capable of only PCI-X 66MHz operation so the bus is initialized to PCI-X 66MHz mode. If PI7C9X110 sees logic HIGH on PCIXCAP, then all devices on the secondary bus are capable of PCI-X 100MHz or 133MHz operation. Since PI7C9X110 does not have a pin to distinguish between the 100MHz or 133MHz clock frequencies, its logic is based on 133MHz. The secondary bus is initialized to PCI-X 133MHz mode. However, 100MHz clock can still be used if all the devices on the PCI-X bus are 100MHz capable and the clock input (pin CLKIN) is set at 100MHz frequency. There is no pin for M66EN for the secondary interface of PI7C9X110 because the internal PLL is bypassed in conventional PCI mode. CLKIN is used directly, eliminating the need to distinguish between conventional PCI 33MHz and 66MHz. Figure 3-1 PCI / PCI-X Selection
PI7C9X110
3.3v 56K Ohms PCIXCAP 1K Ohms Strong Pull-up 0.01uF PCIXUP 10K Ohms 0.01uF 0.01uF Weak Pull-up
Enable During Bus Capability Determination
3.3v
PCI Card
PCI-X 66MHz Card
PCI-X 100MHz or 133MHz Card
3.3
PIN STRAPPING
If TM2 is strapped to high, PI7C9X110 uses TM1, TM0, and MSK_IN as strapping pins. The strapping functions are listed in Table 3-2 to show the states of operations during the PCI Express PERST_L de-assertion transition in forward bridge mode or PCI RESET_L de-assertion transition in reverse bridge mode. Table 3-2 Pin Strapping
TM2 Strapped TM1 Strapped TM0 Strapped MSK_IN Strapped Test Functions
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PI7C9X110
PCIe-to-PCI Reversible Bridge
TM2 Strapped 1 1 1 1 1 1 1 1
TM1 Strapped 0 0 1 1 0 0 1 1
TM0 Strapped 0 1 0 1 0 1 0 1
MSK_IN Strapped 1 1 1 1 0 0 0 0
Test Functions PLL test Shorten initialization test with hotplug enabled Functional loopback test Bridge test (PRBS, IDDQ, etc.) Reserved Shorten initialization test with hotplug disabled Reserved Reserved
4
FORWARD AND REVERSE BRIDGING
PI7C9X110 supports forward or reverse and transparent or non-transparent combination modes of operation. For example, when PI7C9X110 is operating in forward (REVRSB=0) and non-transparent bridge mode (TM0=1) shown in Figure 4-1, its PCI Express interface is connected to a root complex and its PCI bus interface is connected to PCI devices. Another example, PI7C9X110 can be configured as a reverse (REVRSB=1) and transparent (TM0=0) bridge shown in Figure 4-2. The non-transparent bridge feature of PI7C9X110 allows the I/O Processor to be isolated from the Host Processor and its memory map which avoiding memory address conflict when both host and I/O processors are needed sideby-side. PCI based systems and peripherals are ubiquitous in the I/O interconnect technology market today. It will be a tremendous effort to convert existing PCI based products to be used in PCI Express systems. PI7C9X110 provides a solution to bridge existing PCI based products to the latest PCI Express technology. Figure 4-1 Forward and Non-transparent Bridge Mode
Host Processor
System Memory
Root Complex
x1 link
PI7C9X110
Local Memory
Local Processor
Fibre Channel
Fast Ethernet
SCSI
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PI7C9X110
PCIe-to-PCI Reversible Bridge
In reverse (REVRSB=1) and transparent (TM0=0) mode shown in Figure 3-2, PI7C9X110 becomes a PCI-to-PCI Express bridge that its PCI bus interface is connected to the host chipset between and the PCI Express x1 link. It enables the legacy PCI Host Systems to provide PCI Express capability. PI7C9X110 provides a solution to convert existing PCI based designs to adapt quickly into PCI Express base platforms. Existing PCI based applications will not have to undergo a complete re-architecture in order to interface to PCI Express technology. Figure 4-2 Reverse and Transparent Bridge Mode
Host Processor
System Memory
Chipset
32bit / 66MHz 32bit / 66MHz
PI7C9X110
Fibre Channel
Fast Ethernet
SCSI
x1 link
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PCIe-to-PCI Reversible Bridge
5
5.1
TRANSPARENT AND NON-TRANSPARENT BRIDGING
TRANSPARENT MODE
In transparent bridge mode, base class code of PI7C9X110 is set to be 06h (bridge device). The sub-class code is set to be 04h (PCI-to-PCI bridge). Programming interface is 00h. Hence, PI7C9X110 is not a subtractive decoding bridge. PI7C9X110 has type-1 configuration header if TM0 is set to 0 (transparent bridge mode). These configuration registers are the same as traditional transparent PCI-to-PCI Bridge. In fact, it is backward compatible to the software that supporting traditional transparent PCI-to-PCI bridges. Configuration registers can be accessed from several different ways. For PCI Express access, PCI Express configuration transaction is in forward bridge mode. For PCI access, PCI configuration cycle is mainly in reverse bridge mode. However, PI7C9X110 allows PCI configuration access in forward mode as secondary bus configuration access. For I2C access, I2C bus protocol is used with EEPROM selected (TM1=0). For SM bus access, SM bus protocol is used with SM bus selected (TM1=1).
5.2
NON-TRANSPARENT MODE
In non-transparent bridge mode, base class code of PI7C9X110 is set to be 06h (bridge device). The sub-class code is set to be 80h (other bridge). Programming interface is 00h. Hence, PI7C9X110 is not a subtractive decoding bridge. PI7C9X110 has type-0 configuration header if TM0 is set to 1 (non-transparent mode). The configuration registers are similar to a traditional PCI device. However, there is one set of configuration registers for the primary interface and another set of configuration registers for the secondary interface. In addition, CSRs (Control and Status Registers) are implemented to support the memory or IO transfers between the primary and secondary buses. The CSRs are accessed through memory transaction access within the lowest memory range of 4K Space (bit [64:12] are zeros). The non-transparent configuration registers can be accessed through several different ways (PCI Express, PCI, I2C, and SM bus). For PCI Express and PCI access, the type-0 configuration transactions need to be used. For I2C access, I2C bus protocol needs to be used through I2C bus interface. For SM bus access, SM bus protocol needs to be used through SM bus interface. The hardware pins (A2 and A1) are shared for I2C and SM bus interface. If TM1=0, pin A2 and A1 will be SCL and SDA for I2C interface respectively. If TM1=1, pin A2 and A1 will be SMBCLK and SMBDATA for SM Bus interface respectively. In non-transparent bridge mode, PI7C9X110 supports four or three memory BARs (Base Address Registers) and one or two IO BARs (Base Address Registers) depending on selection on the primary bus. Also, PI7C9X110 supports four or three memory BARs (Base Address Registers) and one or two IO BARs (Base Address Registers) depending on selection on the secondary bus. Offset 10h is defined to be primary CSR and downstream memory 0 BAR. Offset 14h is defined to be primary CSR and downstream IO BAR. Offset 18h is defined to be downstream memory 1 or IO BAR (selectable by CSR setup register). Offset 1Ch is defined to be downstream memory 2 BAR. Offset 20h and 24h are defined to be downstream memory 3 lower BAR and memory 3 upper BAR respectively to support 64-bit decoding. The direct offset translation of address from primary to secondary bus will be done by substituting the original Base Address at primary with the downstream Translation Base Address Register values and keeping the lower address bits the same to form a new address for forward the transaction to secondary bus. For downstream memory 2, it uses direct address translation. There is no lookup table for downstream memory address translation.
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PCIe-to-PCI Reversible Bridge
Offset 50h is defined to be secondary CSR and upstream memory 0 BAR. Offset 54h is defined to be secondary CSR and upstream IO BAR. Offset 58h is defined to be upstream memory 1 or IO BAR (selectable by CSR setup register offset E4h). Offset 1Ch is defined to be upstream memory 2 BAR. Offset 60h and 64h are defined to be upstream memory 3 lower BAR and memory 3 upper BAR respectively to support 64-bit decoding. The direct offset translation of address from secondary to primary bus will be done by substituting the original Base Address at secondary with the upstream Translation Base Address Register values and keeping the lower address bits the same to form a new address for forward the transaction to primary bus. For upstream memory 2, it uses lookup table address translation method which using the original base address as index to select a new address on the upstream memory 2 lookup table based on the page and window size defined. Table 5-1 Non-transparent Registers
Non-transparent Registers Primary CSR and Memory 0 BAR Downstream Memory 0 Translated Base Downstream Memory 0 Setup Downstream I/O or Memory 1 BAR Downstream I/O or Memory 1 Translated Base Downstream I/O or Memory 1 Setup Downstream Memory 2 BAR Downstream Memory 2 Translated Base Downstream Memory 2 Setup Downstream Memory 3 BAR Downstream Memory 3 Upper 32-bit BAR Downstream Memory 3 Translated Base Downstream Memory 3 Setup Downstream Memory 3 Upper 32-bit Setup Secondary CSR Memory 0 BAR Upstream Memory 0 Translated Base Upstream Memory 0 Setup Secondary CSR I/O BAR Upstream I/O or Memory 1 BAR Upstream I/O or Memory 1 Translated Base Upstream I/O or Memory 1 Setup Upstream Memory 2 BAR Upstream Memory 2 Lookup Table Offset Upstream Memory 2 Lookup Table Data Upstream Memory 2 Lookup Table (64 32-bit entries) Upstream Memory 3 BAR Upstream Memory 3 Upper 32-bit BAR Upstream Memory 3 Setup Upstream Memory 3 Upper 32-bit Setup Typical access Configuration access offset 10h Configuration access offset 98h Configuration access offset 9Ch Configuration access offset 18h Configuration access offset A8h Configuration access offset ACh Configuration access offset 1Fh Lower 4K I/O or Memory access offset 008h Lower 4K I/O or Memory access offset 00Ch Configuration access offset 23h Configuration access offset 27h Lower 4K I/O or Memory access offset 010h Lower 4K I/O or Memory access offset 014h Lower 4K I/O or Memory access offset 018h Configuration access offset 50h Configuration access offset E0h Configuration access offset E4h Configuration access offset 54h Configuration access offset 58h Configuration access offset E8h Configuration access offset ECh Configuration access offset 5Fh Lower 4K I/O or Memory access offset 050h Lower 4K I/O or Memory access offset 054h Lower 4K I/O or Memory access offset 100h to 1FFh Configuration access offset 63h Configuration access offset 67h Lower 4K I/O or Memory access offset 34h Lower 4K I/O or Memory access offset 38h
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PI7C9X110
PCIe-to-PCI Reversible Bridge
6
6.1
PCI EXPRESS FUNCTIONAL OVERVIEW
TLP STRUCTURE
PCI Express TLP (Transaction Layer Packet) Structure is comprised of format, type, traffic class, attributes, TLP digest, TLP poison, and length of data payload. There are four TLP formats defined in PI7C9X110 based on the states of FMT [1] and FMT [0] as shown on Table 6-1. Table 6-1 TLP Format
FMT [1] 0 0 1 1 FMT [0] 0 1 0 1 TLP Format 3 double word, without data 4 double word, without data 3 double word, with data 4 double word, with data
Data payload of PI7C9X110 can range from 4 (1DW) to 256 (64DW) bytes. PI7C9X110 supports three TLP routing mechanisms. They are comprised of Address, ID, and Implicit routings. Address routing is being used for Memory and IO requests. ID based (bus, device, function numbers) routing is being used for configuration requests. Implicit routing is being used for message routing. There are two message groups (baseline and advanced switching). The baseline message group contains INTx interrupt signaling, power management, error signaling, locked transaction support, slot power limit support, vendor defined messages, hot-plug signaling. The other is advanced switching support message group. The advanced switching support message contains data packet and signal packet messages. Advanced switching is beyond the scope of PI7C9X110 implementation. The r [2:0] values of the "type" field will determine the destination of the message to be routed. All baseline messages must use the default traffic class zero (TC0).
6.2
VIRTUAL ISOCHRONOUS OPERATION
This section provides a summary of Virtual Isochronous Operation supported by PI7C9X110. Virtual Isochronous support is disabled by default. Virtual Isochronous feature can be turned on with setting bit [26] of offset 40h to one. Control bits are designated for selecting which traffic class (TC1-7) to be used for upstream (PCI Express-toPCI). PI7C9X110 accepts only TC0 packets of configuration, IO, and message packets for downstream (PCI Express-to-PCI). If configuration, IO and message packets have traffic class other than TC0, PI7C9X110 will treat them as malformed packets. PI7C9X110 maps all downstream memory packets from PCI Express to PCI transactions regardless the virtual Isochronous operation is enabled or not.
7
CONFIGURATION REGISTERS
PI7C9X110 supports Type-0 (non-transparent bridge mode) and Type-1 (transparent bridge mode) configuration space headers and Capability ID of 01h (PCI power management) to 10h (PCI Express capability structure). With pin REVRSB = 0, device-port type (bit [7:4]) of capability register will be set to 7h (PCI Express-to-PCI/PICX bridge). When pin REVRSB = 1, device-port type (bit [7:4]) of capability register will be set to 8h (PCI/PCI-Xto-PCI Express bridge). PI7C9X110 supports PCI Express capabilities register structure with capability version set to 1h (bit [3:0] of offset 02h).
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PCIe-to-PCI Reversible Bridge
When pin TM0=0, PI7C9X110 will be in transparent bridge mode and the configuration registers for transparent bridge should be used. When pin TM0=1, PI7C9X110 will be in non-transparent bridge mode and the configuration registers for nontransparent bridge should be used.
7.1
CONFIGURATION REGISTER MAP
PI7C9X110 supports capability pointer with PCI-X (ID=07h), PCI power management (ID=01h), PCI bridge subsystem vendor ID (ID=0Dh), PCI Express (ID=10h), vital product data (ID=03h), and message signaled interrupt (ID=05h). Slot identification (ID=04h) is off by default and can be turned on through configuration programming. Table 7-1 Configuration Register Map (00h - FFh)
Primary Bus Configuration Access for both Transparent and Non-Transparent mode, or Secondary Bus Configuration Access for Transparent Mode 01h - 00h 03h - 02h 05h - 04h 07h - 06h 0Bh - 08h 0Ch 0Dh 0Eh 0Fh 13h - 10h 17h - 14h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Fh - 1Eh 21h - 20h 23h - 22h 25h - 24h Secondary Bus Configuration Access for Non-Transparent Mode Only Transparent Mode (type1) Non-Transparent Mode (Type0) EEPROM (I2C) Access SM Bus Access
01h - 00h 03h - 02h 45h - 44h 47h - 46h 0Bh - 08h 4Ch 4Dh 4Eh 4Fh 53h - 50h 57h - 54h 58h 59h 5Ah 5Bh 5Ch 5Dh 5Fh - 5Eh 61h - 60h 63h - 62h 65h - 64h
Vendor ID Device ID Command Register Primary Status Register Class Code and Revision ID Cacheline Size Register Primary Latency Timer Header Type Register Reserved Reserved Reserved Primary Bus Number Register Secondary Bus Number Register Subordinate Bus Number Register Secondary Latency Timer I/O Base Register I/O Limit Register Secondary Status Register Memory Base Register Memory Limit Register Prefetchable Memory Base Register
Vendor ID Device ID Primary Command Register Primary Status Register Class Code and Revision ID Primary Cacheline Size Register Primary Latency Timer Header Type Register Reserved Primary CSR and Memory 0 BAR Primary CSR I/O BAR Downstream I/O or Memory 1 BAR Downstream I/O or Memory 1 BAR Downstream I/O or Memory 1 BAR Downstream I/O or Memory 1 BAR Downstream Memory 2 BAR Downstream Memory 2 BAR Downstream Memory 2 BAR Downstream Memory 3 BAR Downstream Memory 3 BAR Downstream Memory 3 Upper 32-bit BAR
Yes1 Yes1 No No Yes1 No No No No No No No No No No No No No No
Yes5 Yes5 Yes Yes Yes5 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
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PCIe-to-PCI Reversible Bridge
Primary Bus Configuration Access for both Transparent and Non-Transparent mode, or Secondary Bus Configuration Access for Transparent Mode 27h - 26h 2Bh - 28h
Secondary Bus Configuration Access for Non-Transparent Mode Only
Transparent Mode (type1)
Non-Transparent Mode (Type0)
EEPROM (I2C) Access
SM Bus Access
67h - 66h 2Bh - 28h
2Dh - 2Ch
2Dh - 2Ch
2Fh - 2Eh
2Fh - 2Eh
31h - 30h 33h - 32h 34h 37h - 35h 3Bh - 38h 3Ch 3Dh 3Eh 3Fh 41h - 40h 43h - 42h 45h - 44h 47h - 46h 4Bh - 48h 4Ch 4Dh 4Eh 4Fh 53h - 50h 57h - 54h 5Bh - 58h 5Fh - 5Ch 63h - 60h 67h - 64h 69h - 68h 6Ah 6Bh 6Dh - 6Ch 6Fh - 6Eh
31h - 30h 33h - 32h 34h 37h - 35h 3Bh - 38h 7Ch 7Dh 7Eh 7Fh 41h - 40h 43h - 42h 05h - 04h 07h - 06h 4Bh - 48h 0Ch 0Dh 0Eh 0Fh 13h - 10h 17h - 14h 1Bh - 18h 1Fh - 1Ch 23h - 20h 27h - 24h 69h - 68h 6Ah 6Bh 6Dh - 6Ch 6Fh - 6Eh
Prefetchable Memory Limit Register Prefetchable Memory Base Upper 32-bit Register Prefetchable Memory Limit Upper 32-bit Register Prefetchable Memory Limit Upper 32-bit Register I/O Base Upper 16-bit Register I/O Limit Upper 16-bit Register Capability Pointer Reserved Reserved Interrupt Line Interrupt Pin Bridge Control Bridge Control PCI Data Buffering Control Chip Control 0 Reserved Reserved Arbiter Mode, Enable, Priority Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved PCI Express Tx and Rx Control Reserved Reserved Reserved Reserved
Downstream Memory 3 Upper 32-bit BAR
No No
Yes Yes
Subsystem Vendor ID
Yes2
Yes5
Subsystem ID
Yes2
Yes5
Reserved Reserved Capability Pointer Reserved Reserved Primary Interrupt Line Primary Interrupt Pin Primary Min_Gnt Primary Max_Lat PCI Data Buffering Control Chip Control 0 Secondary Command Register Secondary Status Register Arbiter Mode, Enable, Priority Secondary Cacheline Size Register Secondary Status Register Header Type Reserved Secondary CSR and Memory 0 BAR Secondary CSR I/O BAR Upstream I/O or Memory 1 BAR Upstream Memory 2 BAR Upstream Memory 3 BAR Upstream Memory 3 Upper 32-bit BAR PCI Express Tx and Rx Control Memory Address Forwarding Control Reserved Subsystem Vendor ID Subsystem ID
No No No No No No No Yes3 Yes3 Yes Yes No No Yes No No No No No No No No No Yes Yes3 No Yes2 Yes2
Yes Yes Yes Yes Yes Yes Yes Yes3 Yes3 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes3 Yes Yes5 Yes5
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PCIe-to-PCI Reversible Bridge
Primary Bus Configuration Access for both Transparent and Non-Transparent mode, or Secondary Bus Configuration Access for Transparent Mode 73h - 70h
Secondary Bus Configuration Access for Non-Transparent Mode Only
Transparent Mode (type1)
Non-Transparent Mode (Type0)
EEPROM (I2C) Access
SM Bus Access
73h - 70h
77h - 74h 7Bh - 78h 7Bh - 78h 7Bh - 78h 7Ch 7Dh 7Eh 7Fh 83h - 80h 87h - 84h 8Bh - 88h 8Fh - 8Ch 93h - 90h 97h - 94h 9Bh - 98h 9Fh - 9Ch A3h - A0h A7h - A4h ABh - A8h
77h - 74h 7Bh - 78h 7Bh - 78h 7Bh - 78h 3Ch 3Dh 3Eh 3Fh 83h - 80h 87h - 84h 8Bh - 88h 8Fh - 8Ch 93h - 90h 97h - 94h 9Bh - 98h 9Fh - 9Ch A3h - A0h A7h - A4h ABh - A8h
EEPROM (I2C) Control and Status Register Reserved GPIO Data and Control (20 bits) Reserved (12 bits) Reserved (12 bits) Reserved Reserved Reserved Reserved PCI-X Capability PCI-X Bridge Status Upstream Split Transaction Downstream Split Transaction Power Management Capability Power Management Control and Status Reserved Reserved Slot ID Capability PCI Clock and CLKRUN Control SSID and SSVID Capability Subsystem ID and Subsystem Vendor ID PCI Express Capability Device Capability Device Control and Status Link Capability Link Control and Status Slot Capability Slot Control and Status XPIP Configuration Register 0 XPIP Configuration Register 1 XPIP Configuration Register 2 Reserved VPD Capability Register VPD Data Register
Afh - ACh B3h - B0h B7h - B4h BBh - B8h BFh - BCh C3h - C0h C7h - C4h CBh - C8h CFh - CCh D3h - D0h D6h - D4h D7h DBh - D8h DFh - DCh
Afh - ACh B3h - B0h B7h - B4h BBh - B8h BFh - BCh C3h - C0h C7h - C4h CBh - C8h CFh - CCh D3h - D0h D6h - D4h D7h DBh - D8h DFh - DCh
EEPROM (I2C) Control and status Register Reserved GPIO Data and Control (20 bits) Bridge Control and Status (10 bits) Reserved (2 bits) Secondary Interrupt Line Secondary Interrupt Pin Secondary Min_Gnt Secondary Max_Lat PCI-X Capability PCI-X Bridge Status Upstream Split Transaction Downstream Split Transaction Power Management Capability Power Management Control and Status Downstream Memory 0 Translated Base Downstream Memory 0 Setup Slot ID Capability PCI Clock and CLKRUN Control Downstream I/O or Memory 1 Translated Base Downstream I/O or Memory 1 Setup PCI Express Capability Device Capability Device Control and Status Link Capability Link Control and Status Slot Capability Slot Control and Status XPIP Configuration Register 0 XPIP Configuration Register 1 XPIP Configuration Register 2 Reserved VPD Capability Register VPD Data Register
No
Yes
No No No No No No Yes3 Yes3 No No No No Yes No No Yes
3
Yes Yes No No Yes Yes Yes3 Yes3 Yes Yes Yes Yes Yes Yes Yes Yes3 Yes Yes Yes
No Yes No
Yes No Yes No Yes No No No Yes Yes Yes Yes No Yes4
Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
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PCIe-to-PCI Reversible Bridge
Primary Bus Configuration Access for both Transparent and Non-Transparent mode, or Secondary Bus Configuration Access for Transparent Mode E3h - E0h E7h - E4h EBh - E8h
Secondary Bus Configuration Access for Non-Transparent Mode Only
Transparent Mode (type1)
Non-Transparent Mode (Type0)
EEPROM (I2C) Access
SM Bus Access
E3h - E0h E7h - E4h EBh - E8h
Reserved Reserved Reserved
EFh - ECh F3h - F0h F7h - F4h FBh - F8h
EFh - ECh F3h - F0h F7h - F4h FBh - F8h
Reserved MSI Capability Register Message Address Message Upper Address Message Date
FFh - FCh FFh - FCh Note 1: When masquerade is enabled, it is pre-loadable. Note 2: When both masquerade and non-transparent mode are enabled, it is pre-loadable. Note 3: When non-transparent mode is enabled, it is pre-loadable. Note 4: The VPD data is read/write through I2C during VPD operation. Note 5: Read access only.
Upstream Memory 0 Translated Base Upstream Memory 0 setup Upstream I/O or Memory 1 Translated Base Upstream I/O or Memory 1 Setup MSI Capability Register Message Address Message Upper Address Message Date
No Yes3 No Yes3 No No No No
Yes Yes3 Yes Yes3 Yes Yes Yes Yes
7.2
PCI EXPRESS EXTENDED CAPABILITY REGISTER MAP
PI7C9X110 also supports PCI Express Extended Capabilities with from 257-byte to 4096-byte space. The offset range is from 100h to FFFh. The offset 100h is defined for Advance Error Reporting (ID=0001h). The offset 150h is defined for Virtual Channel (ID=0002h). Table 7-2 PCI Express Extended Capability Register Map (100h - FFFh)
Primary Bus Configuration Access for both Transparent and Non-Transparent mode, or Secondary Bus Configuration Access for Transparent Mode 103h - 100h Secondary Bus Configuration Access for Non-Transparent Mode Only Transparent Mode (type1) Non-Transparent Mode (Type0) EEPROM (I2C) Access SM Bus Access
103h - 100h
107h - 104h 10Bh - 108h 10Fh - 10Ch 113h - 110h 117h - 114h 11Bh - 118h 12Bh - 11Ch 12Fh - 12Ch
107h - 104h 10Bh - 108h 10Fh - 10Ch 113h - 110h 117h - 114h 11Bh - 118h 12Bh - 11Ch 12Fh - 12Ch
Advanced Error Reporting (AER) Capability Uncorrectable Error Status Uncorrectable Error Mask Uncorrectable Severity Correctable Error Status Correctable Error Mask AER Control Header Log Register Secondary Uncorrectable Error Status
Advanced Error Reporting (AER) Capability Uncorrectable Error Status Uncorrectable Error Mask Uncorrectable Severity Correctable Error Status Correctable Error Mask AER Control Header Log Register Secondary Uncorrectable Error Status
No
Yes5
No No No No No No No No
Yes Yes Yes Yes Yes Yes Yes Yes
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PCIe-to-PCI Reversible Bridge
Primary Bus Configuration Access for both Transparent and Non-Transparent mode, or Secondary Bus Configuration Access for Transparent Mode 133h - 130h
Secondary Bus Configuration Access for Non-Transparent Mode Only
Transparent Mode (type1)
Non-Transparent Mode (Type0)
EEPROM (I2C) Access
SM Bus Access
133h - 130h
137h - 134h 13Bh - 138h 14Bh - 13Ch 14Fh - 14Ch 153h - 150h 157h - 154h 15Bh - 158h 15Fh - 15Ch 163h - 160h 167h - 164h 16Bh - 168h 2FFh - 170h 303h - 300h 307h - 304h 30Fh - 308h 310h
137h - 134h 13Bh - 138h 14Bh - 13Ch 14Fh - 14Ch 153h - 150h 157h - 154h 15Bh - 158h 15Fh - 15Ch 163h - 160h 167h - 164h 16Bh - 168h 2FFh - 170h 503h - 500h 507h - 504h 50Fh - 508h 510h
4FFh - 314h 503h - 500h 504h 50Fh - 505h 510h FFFh - 514h Note 5: Read access only.
4FFh - 314h 303h - 300h 304h 30Fh - 305h 310h FFFh - 514h
Secondary Uncorrectable Error Mask Secondary Uncorrectable Severity Secondary AER Control Secondary Header Log Register Reserved VC Capability Port VC Capability 1 Port VC Capability 2 Port VC Status and Control VC0 Resource Capability VC0 Resource Control VC0 Resource Status Reserved Reserved Extended GPI/GPO Data and Control Reserved Replay and Acknowledge Latency Timer Reserved Reserved Reserved Reserved Reserved Reserved
Secondary Uncorrectable Error Mask Secondary Uncorrectable Severity Secondary AER Control Secondary Header Log Register Reserved VC Capability Port VC Capability 1 Port VC Capability 2 Port VC Status and Control VC0 Resource Capability VC0 Resource Control VC0 Resource Status Reserved Reserved Extended GPI/GPO Data and Control Reserved Replay and Acknowledge Latency Timer Reserved Reserved Reserved Reserved Reserved Reserved
No
Yes
No No No No No No No No No No No No No No No Yes
Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No Yes Yes No Yes
No No No No No No
No No No No No No
7.3
CONTROL AND STATUS REGISTER MAP
Table 7-3 Control and Status Register (CSR) Map (000h - FFFh)
PCI Express / PCI Memory Offset 007h - 000h 00Bh - 008h 00Fh - 00Ch 013h - 010h 017h - 014h 01Bh - 018h 02Fh - 01Ch SM Bus Offset Register Name Reset Value EEPROM (I2C) Access No No Yes No Yes Yes No SM Bus Access Yes Yes Yes Yes Yes Yes Yes
207h - 200h 20Bh - 208h 20Fh - 20Ch 213h - 210h 217h - 214h 21Bh - 218h 22Fh - 21Ch
Reserved Downstream Memory 2 Translated Base Downstream Memory 2 Setup Downstream Memory 3 Translated Base Downstream Memory 3 Setup Downstream Memory 3 Upper 32-bit Setup Reserved
0 XXXX_XXXXh 0000_0000h XXXX_XXXXh 0000_0000h 0000_0000h 0
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PCIe-to-PCI Reversible Bridge
PCI Express / PCI Memory Offset 033h - 030h 037h - 034h 03Bh - 038h 04Fh - 03Ch 050h 053h - 051h 057h - 054h 05Bh - 058h 05Fh - 05Ch 063h - 060h 067h - 064h 06Fh - 068h 071h - 070h 073h - 072h 075h - 074h 077h - 076h 079h - 078h 07Bh - 07Ah 07Dh - 07Ch 07Fh - 07Eh 09Fh - 080h 0A3h - 0A0h 0A7h - 0A4h 0ABh - 0A8h 0AFh - 0ACh 0B3h - 0B0h 0B7h - 0B4h 0BBh - 0B8h 0BFh - 0BCh 0FFh - 0C0h 1FFh - 100h FFFh - 200h
SM Bus Offset
Register Name
Reset Value
233h - 230h 237h - 234h 21Bh - 218h 24Fh - 23Ch 250h 253h - 251h 257h - 254h 25Bh - 258h 25Fh - 25Ch 263h - 260h 267h - 264h 26Fh - 268h 271h - 270h 273h - 272h 275h - 274h 277h - 276h 279h - 278h 27Bh - 27Ah 27Dh - 27Ch 27Fh - 27Eh 29Fh - 280h 2A3h - 2A0h 2A7h - 2A4h 2ABh - 2A8h 2AFh - 2ACh 2B3h - 2B0h 2B7h - 2B4h 2BBh - 2B8h 2BCh - 2BFh 2FFh - 2C0h 3FFh - 300h 11FFh - 400h
Reserved Upstream Memory 3 Setup Upstream Memory 3 Upper 32-bit Setup Reserved Lookup Table Offset Register Reserved Lookup Table Data Register Upstream Page Boundary IRQ 0 Upstream Page Boundary IRQ 1 Upstream Page Boundary IRQ Mask 0 Upstream Page Boundary IRQ Mask 1 Reserved Primary Clear IRQ Register Secondary Clear IRQ Register Primary Set IRQ Register Secondary Set IRQ Register Primary Clear IRQ Mask Register Secondary Clear IRQ Mask Register Primary Set IRQ Mask Register Secondary Set IRQ Mask Register Reserved Scratch pad 0 Scratch pad 1 Scratch pad 2 Scratch pad 3 Scratch pad 4 Scratch pad 5 Scratch pad 6 Scratch pad 7 Reserved Upstream Memory 2 Lookup Table Reserved
X 0000_0000h 0000_0000h 0 XXh 0 XXXX_XXXXh 0000_0000h 0000_0000h FFFF_FFFFh FFFF_FFFFh 0 0000h 0000h 0000h 0000h FFFFh FFFFh FFFFh FFFFh 0 XXXX_XXXXh XXXX_XXXXh XXXX_XXXXh XXXX_XXXXh XXXX_XXXXh XXXX_XXXXh XXXX_XXXXh XXXX_XXXXh 0 0 0
EEPROM (I2C) Access No Yes Yes No No No No No No No No No No No No No No No No No No No No No No No No No No No No No
SM Bus Access Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
7.4
PCI CONFIGURATION REGISTERS FOR TRANSPARENT BRIDGE MODE
The following section describes the configuration space when the device is in transparent mode. The descriptions for different register type are listed as follow:
Register Type RO ROS RW Descriptions Read Only Read Only and Sticky Read/Write
Page 32 of 145 Pericom Semiconductor November 2007, Revision 2.4
PI7C9X110
PCIe-to-PCI Reversible Bridge
RWC RWS RWCS
Read/Write "1" to clear Read/Write and Sticky Read/Write "1" to clear and Sticky
7.4.1
VENDOR ID - OFFSET 00h
BIT 15:0 FUNCTION Vendor ID TYPE RO DESCRIPTION Identifies Pericom as the vendor of this device. Returns 12D8h when read.
7.4.2
DEVICE ID - OFFSET 00h
BIT 31:16 FUNCTION Device ID TYPE RO DESCRIPTION Identifies this device as the PI7C9X110. Returns E110 when read.
7.4.3
COMMAND REGISTER - OFFSET 04h
BIT 0 FUNCTION I/O Space Enable TYPE RW DESCRIPTION 0: Ignore I/O transactions on the primary interface 1: Enable response to memory transactions on the primary interface Reset to 0 0: Ignore memory read transactions on the primary interface 1: Enable memory read transactions on the primary interface Reset to 0 0: Do not initiate memory or I/O transactions on the primary interface and disable response to memory and I/O transactions on the secondary interface 1: Enable the bridge to operate as a master on the primary interfaces for memory and I/O transactions forwarded from the secondary interface. If the primary of the reverse bridge is PCI-X mode, the bridge is allowed to initiate a split completion transaction regardless of the status bit. Reset to 0 0: PI7C9X110 does not respond as a target to Special Cycle transactions, so this bit is defined as Read-Only and must return 0 when read Reset to 0 0: PI7C9X110 does not originate a Memory Write and Invalidate transaction. Implements this bit as Read-Only and returns 0 when read (unless forwarding a transaction for another master). This bit will be ignored in PCI-X mode. Reset to 0 This bit applies to reverse bridge only. 0: Ignore VGA palette access on the primary 1: Enable positive decoding response to VGA palette writes on the primary interface with I/O address bits AD [9:0] equal to 3C6h, 3C8h, and 3C9h (inclusive of ISA alias; AD [15:0] are not decoded and may be any value) Reset to 0 0: May ignore any parity error that is detected and take its normal action 1: This bit if set, enables the setting of Master Data Parity Error bit in the Status Register when poisoned TLP received or parity error is detected and takes its normal action Reset to 0 Wait cycle control not supported Reset to 0 0: Disable 1: Enable PI7C9X110 in forward bridge mode to report non-fatal or fatal error message to the Root Complex. Also, in reverse bridge mode to assert
1
Memory Space Enable
RW
2
Bus Master Enable
RW
3
Special Cycle Enable
RO
4
Memory Write and Invalidate Enable
RO
5
VGA Palette Snoop Enable
RO / RW
6
Parity Error Response Enable
RW
7
Wait Cycle Control
RO
8
SERR_L Enable Bit
RW
Page 33 of 145 Pericom Semiconductor November 2007, Revision 2.4
PI7C9X110
PCIe-to-PCI Reversible Bridge
BIT
FUNCTION
TYPE
DESCRIPTION SERR_L on the primary interface Reset to 0 Fast back-to-back enable not supported Reset to 0 This bit applies to reverse bridge only. 0: INTA_L, INTB_L, INTC_L, and INTD_L can be asserted on PCI interface 1: Prevent INTA_L, INTB_L, INTC_L, and INTD_L from being asserted on PCI interface Reset to 0 Reset to 00000
9
Fast Back-to-Back Enable
RO
10
Interrupt Disable
RO / RW
15:11
Reserved
RO
7.4.4
PRIMARY STATUS REGISTER - OFFSET 04h
BIT 18:16 19 20 FUNCTION Reserved Reserved (transparent mode) Capability List Capable TYPE RO RO RO DESCRIPTION Reset to 000 Reset to 0 1: PI7C9X110 supports the capability list (offset 34h in the pointer to the data structure) Reset to 1 This bit applies to reverse bridge only. 1: 66MHz capable Reset to 0 when forward bridge or 1 when reverse bridge. Reset to 0 This bit applies to reverse bridge only. 1: Enable fast back-to-back transactions Reset to 0 when forward bridge or 1 when reverse bridge in PCI mode. Bit set if its Parity Error Enable bit is set and either of the conditions occurs on the primary: FORWARD BRIDGE - Receives a completion marked poisoned Poisons a write request REVERSE BRIDGE - Detected parity error when receiving data or Split Response for read Observes P_PERR_L asserted when sending data or receiving Split Response for write Receives a Split Completion Message indicating data parity error occurred for non-posted write Reset to 0 These bits apply to reverse bridge only. 00: 01: 10: 11: fast DEVSEL_L decoding medium DEVSEL_L decoding slow DEVSEL_L decoding reserved
21
66MHz Capable
RO
22 23
Reserved Fast Back-to-Back Capable
RO RO
24
Master Data Parity Error Detected
RWC
26:25
DEVSEL_L Timing (medium decode)
RO
27
Signaled Target Abort
RWC
Reset to 00 when forward bridge or 01 when reverse bridge. FORWARD BRIDGE - This bit is set when PI7C9X110 completes a request using completer abort status on the primary REVERSE BRIDGE - This bit is set to indicate a target abort on the primary Reset to 0 FORWARD BRIDGE -
28
Received Target Abort
RWC
Page 34 of 145 Pericom Semiconductor November 2007, Revision 2.4
PI7C9X110
PCIe-to-PCI Reversible Bridge
BIT
FUNCTION
TYPE
DESCRIPTION This bit is set when PI7C9X110 receives a completion with completer abort completion status on the primary REVERSE BRIDGE - This bit is set when PI7C9X110 detects a target abort on the primary Reset to 0 FORWARD BRIDGE - This bit is set when PI7C9X110 receives a completion with unsupported request completion status on the primary REVERSE BRIDGE - This bit is set when PI7C9X110 detects a master abort on the primary FORWARD BRIDGE - This bit is set when PI7C9X110 sends an ERR_FATAL or ERR_NON_FATAL message on the primary REVERSE BRIDGE - This bit is set when PI7C9X110 asserts SERR_L on the primary Reset to 0 FORWARD BRIDGE - This bit is set when poisoned TLP is detected on the primary REVERSE BRIDGE - This bit is set when address or data parity error is detected on the primary Reset to 0
29
Received Master Abort
RWC
30
Signaled System Error
RWC
31
Detected Parity Error
RWC
7.4.5
REVISION ID REGISTER - OFFSET 08h
BIT 7:0 FUNCTION Revision TYPE RO DESCRIPTION Reset to 00000002h
7.4.6
CLASS CODE REGISTER - OFFSET 08h
BIT 15:8 FUNCTION Programming Interface TYPE RO DESCRIPTION Subtractive decoding of PCI-PCI bridge not supported Reset to 00000000 Sub-Class Code 00000100: PCI-to-PCI bridge Reset to 00000100 Base class code 00000110: Bridge Device (transparent mode) Reset to 00000110 (transparent mode)
23:16
Sub-Class Code
RO
31:24
Base Class Code
RO
7.4.7
CACHE LINE SIZE REGISTER - OFFSET 0Ch
BIT 1:0 FUNCTION Reserved TYPE RO DESCRIPTION Bit [1:0] not supported Reset to 00 1: Cache line size = 4 double words Reset to 0 1: Cache line size = 8 double words Reset to 0 1: Cache line size = 16 double words
2
Cache Line Size
RW
3
Cache Line Size
RW
4
Cache Line Size
RW
Page 35 of 145 Pericom Semiconductor November 2007, Revision 2.4
PI7C9X110
PCIe-to-PCI Reversible Bridge
BIT 5
FUNCTION Cache Line Size
TYPE RW
DESCRIPTION Reset to 0 1: Cache line size = 32 double words Reset to 0 Bit [7:6] not supported Reset to 00
7:6
Reserved
RO
7.4.8
PRIMARY LATENCY TIMER REGISTER - OFFSET 0Ch
BIT 15:8 FUNCTION Primary Latency Timer TYPE RO / RW DESCRIPTION 8 bits of primary latency timer in PCI/PCI-X FORWARD BRIDGE - RO with reset to 00h REVERSE BRIDGE - RW with reset to 00h in PCI mode or 40h in PCI-X mode
7.4.9
PRIMARY HEADER TYPE REGISTER - OFFSET 0Ch
BIT 22:16 FUNCTION PCI-to-PCI bridge configuration (transparent mode) Other bridge configuration (non-transparent mode) Single Function Device TYPE RO DESCRIPTION PCI-to-PCI bridge configuration (10 - 3Fh) Reset to 0000001 (transparent mode)
RO RO
23
Type-0 header format configuration (10-3Fh) Reset to 0000000 (non-transparent mode) 0: Indicates single function device Reset to 0 Reset to 00h
31:24
Reserved
RO
7.4.10 RESERVED REGISTERS - OFFSET 10h TO 17h 7.4.11 PRIMARY BUS NUMBER REGISTER - OFFSET 18h
BIT 7:0 FUNCTION Primary Bus Number TYPE RW DESCRIPTION Reset to 00h
7.4.12 SECONDARY BUS NUMBER REGISTER - OFFSET 18h
BIT 15:8 FUNCTION Secondary Bus Number TYPE RW DESCRIPTION Reset to 00h
7.4.13 SUBORDINATE BUS NUMBER REGISTER - OFFSET 18h
BIT 23:16 FUNCTION Subordinate Bus Number TYPE RW DESCRIPTION Reset to 00h
7.4.14 SECONDARY LATENCY TIME REGISTER - OFFSET 18h
BIT 31:24 FUNCTION Secondary Latency Timer TYPE RW / RO DESCRIPTION Secondary latency timer in PCI / PCI-X mode FORWARD BRIDGE - RW with reset to 00h in PCI mode or 40h in PCI-X mode REVERSE BRIDGE - RO with reset to 00h
Page 36 of 145 Pericom Semiconductor November 2007, Revision 2.4
PI7C9X110
PCIe-to-PCI Reversible Bridge
7.4.15 I/O BASE REGISTER - OFFSET 1Ch
BIT 1:0 FUNCTION 32-bit I/O Addressing Support Reserved I/O Base TYPE RO DESCRIPTION 01: Indicates PI7C9X110 supports 32-bit I/O addressing Reset to 01 Reset to 00 Indicates the I/O base (0000_0000h) Reset to 0000
3:2 7:4
RO RW
7.4.16 I/O LIMIT REGISTER - OFFSET 1Ch
BIT 9:8 FUNCTION 32-bit I/O Addressing Support Reserved I/O Base TYPE RO DESCRIPTION 01: Indicates PI7C9X110 supports 32-bit I/O addressing Reset to 01 Reset to 00 Indicates the I/O Limit (0000_0FFFh) Reset to 0000
11:10 15:12
RO RW
7.4.17 SECONDARY STATUS REGISTER - OFFSET 1Ch
BIT 20:16 21 FUNCTION Reserved 66MHz Capable TYPE RO RO DESCRIPTION Reset to 00000 Indicates PI7C9X110 is 66MHz capable Reset to 1 Reset to 0 FORWARD BRIDGE: reset to 1 when secondary bus is in PCI mode (supports fast back-to-back transactions) or reset to 0 when secondary bus is in PCI-X mode (does not support fast back-to-back transactions) REVERSE BRIDGE: reset to 0 (does not support fast back-to-back transactions) This bit is set if its parity error enable bit is set and either of the conditions occur on the primary: FORWARD BRIDGE - * Detected parity error when receiving data or split response for read * Observes S_PERR_L asserted when sending data or receiving split response for write * Receives a split completion message indicating data parity error occurred for non-posted write REVERSE BRIDGE - * Receives a completion marked poisoned * Poisons a write request Reset to 0 These bits apply to forward bridge only. 01: medium DEVSEL_L decoding Reset to 01 when forward mode or 00 when reverse mode. FORWARD BRIDGE - Bit is set when PI7C9X110 signals target abort REVERSE BRIDGE - Bit is set when PI7C9X110 completes a request using completer abort completion status Reset to 0
22 23
Reserved Fast Back-to-Back Capable
RO RO
24
Master Data Parity Error Detected
RWC
26:25
DEVSEL_L Timing (medium decoding)
RO
27
Signaled Target Abort
RWC
Page 37 of 145 Pericom Semiconductor November 2007, Revision 2.4
PI7C9X110
PCIe-to-PCI Reversible Bridge
BIT 28
FUNCTION Received Target Abort
TYPE RWC
DESCRIPTION FORWARD BRIDGE - Bit is set when PI7C9X110 detects target abort on the secondary interface REVERSE BRIDGE - Bit is set when PI7C9X110 receives a completion with completer abort completion status on the secondary interface Reset to 0 FORWARD BRIDGE - Bit is set when PI7C9X110 detects master abort on the secondary interface REVERSE BRIDGE - Bit is set when PI7C9X110 receives a completion with unsupported request completion status on the primary interface Reset to 0 FORWARD BRIDGE - Bit is set when PI7C9X110 detects SERR_L assertion on the secondary interface REVERSE BRIDGE - Bit is set when PI7C9X110 receives an ERR_FATAL or ERR_NON_FATAL message on the secondary interface Reset to 0 FORWARD BRIDGE - Bit is set when PI7C9X110 detects address or data parity error REVERSE BRIDGE - Bit is set when PI7C9X110 detects poisoned TLP on secondary interface Reset to 0
29
Received Master Abort
RWC
30
Received System Error
RWC
31
Detected Parity Error
RWC
7.4.18 MEMORY BASE REGISTER - OFFSET 20h
BIT 3:0 15:4 FUNCTION Reserved Memory Base TYPE RO RW DESCRIPTION Reset to 0000 Memory Base (80000000h) Reset to 800h
7.4.19 MEMORY LIMIT REGISTER - OFFSET 20h
BIT 19:16 31:20 FUNCTION Reserved Memory Limit TYPE RO RW DESCRIPTION Reset to 0000 Memory Limit (000FFFFFh) Reset to 000h
7.4.20 PREFETCHABLE MEMORY BASE REGISTER - OFFSET 24h
BIT 3:0 FUNCTION 64-bit Addressing Support TYPE RO DESCRIPTION 0001: Indicates PI7C9X110 supports 64-bit addressing Reset to 0001 Prefetchable Memory Base (00000000_80000000h) Reset to 800h
15:4
Prefetchable Memory Base
RW
7.4.21 PREFETCHABLE MEMORY LIMIT REGISTER - OFFSET 24h
BIT FUNCTION TYPE DESCRIPTION
Page 38 of 145 Pericom Semiconductor November 2007, Revision 2.4
PI7C9X110
PCIe-to-PCI Reversible Bridge
BIT 19:16
FUNCTION 64-bit Addressing Support
TYPE RO
DESCRIPTION 0001: Indicates PI7C9X110 supports 64-bit addressing Reset to 0001 Prefetchable Memory Limit (00000000_000FFFFFh) Reset to 000h
31:20
Prefetchable Memory Limit
RW
Page 39 of 145 Pericom Semiconductor November 2007, Revision 2.4
PI7C9X110
PCIe-to-PCI Reversible Bridge
7.4.22 PREFETCHABLE BASE UPPER 32-BIT REGISTER - OFFSET 28h
BIT 31:0 FUNCTION Prefetchable Base Upper 32bit TYPE RW DESCRIPTION Bit [63:32] of prefetchable base Reset to 00000000h
7.4.23 PREFETCHABLE LIMIT UPPER 32-BIT REGISTER - OFFSET 2Ch
BIT 31:0 FUNCTION Prefetchable Limit Upper 32-bit TYPE RW DESCRIPTION Bit [63:32] of prefetchable limit Reset to 00000000h
7.4.24 I/O BASE UPPER 16-BIT REGISTER - OFFSET 30h
BIT 15:0 FUNCTION I/O Base Upper 16-bit TYPE RW DESCRIPTION Bit [31:16] of I/O Base Reset to 0000h
7.4.25 I/O LIMIT UPPER 16-BIT REGISTER - OFFSET 30h
BIT 31:16 FUNCTION I/O Limit Upper 16-bit TYPE RW DESCRIPTION Bit [31:16] of I/O Limit Reset to 0000h
7.4.26 CAPABILITY POINTER - OFFSET 34h
BIT 31:8 7:0 FUNCTION Reserved Capability Pointer TYPE RO RO DESCRIPTION Reset to 0 Capability pointer to 80h Reset to 80h
7.4.27 EXPANSION ROM BASE ADDRESS REGISTER - OFFSET 38h
BIT 31:0 FUNCTION Expansion ROM Base Address TYPE RO DESCRIPTION Expansion ROM not supported. Reset to 00000000h
7.4.28 INTERRUPT LINE REGISTER - OFFSET 3Ch
BIT 7:0 FUNCTION Interrupt Line TYPE RW DESCRIPTION These bits apply to reverse bridge only. For initialization code to program to tell which input of the interrupt controller the PI7C9X110's INTA_L in connected to. Reset to 00000000
Page 40 of 145 Pericom Semiconductor November 2007, Revision 2.4
PI7C9X110
PCIe-to-PCI Reversible Bridge
7.4.29 INTERRUPT PIN REGISTER - OFFSET 3Ch
BIT 15:8 FUNCTION Interrupt Pin TYPE RO DESCRIPTION These bits apply to reverse bridge only. Designates interrupt pin INTA_L, is used Reset to 00h when forward mode or 01h when reverse mode.
7.4.30 BRIDGE CONTROL REGISTER - OFFSET 3Ch
BIT 16 FUNCTION Parity Error Response Enable TYPE RW DESCRIPTION 0: Ignore parity errors on the secondary 1: Enable parity error detection on secondary FORWARD BRIDGE - Controls the response to uncorrectable address attribute and data errors on the secondary REVERSE BRIDGE - Controls the setting of the master data parity error bit in response to a received poisoned TLP from the secondary (PCIe link) Reset to 0 0: Disable the forwarding of SERR_L to ERR_FATAL and ERR_NONFATAL 1: Enable the forwarding of SERR_L to ERR_FATAL and ERR_NONFATAL Reset to 0 (FORWARD BRIDGE) RO bit for REVERSE BRIDGE 0: Forward downstream all I/O addresses in the address range defined by the I/O Base and Limit registers 1: Forward upstream all I/O addresses in the address range defined by the I/O Base and Limit registers that are in the first 64KB of PCI I/O address space (top 768 bytes of each 1KB block) Reset to 0 0: Do not forward VGA compatible memory and I/O addresses from the primary to secondary, unless they are enabled for forwarding by the defined I/O and memory address ranges 1: Forward VGA compatible memory and I/O addresses from the primary and secondary (if the I/O enable and memory enable bits are set), independent of the ISA enable bit 0: Execute 10-bit address decodes on VGA I/O accesses 1: Execute 16-bit address decode on VGA I/O accesses Reset to 0 0: Do not report master aborts (return FFFFFFFFh on reads and discards data on write) 1: Report master abort by signaling target abort if possible or by the assertion of SERR_L (if enabled). Reset to 0 0: Do not force the assertion of RESET_L on secondary PCI bus for forward bridge, or do not generate a hot reset on the PCIe link for reverse bridge 1: Force the assertion of RESET_L on secondary PCI bus for forward bridge, or generate a hot reset on the PCIe link for reverse bridge Reset to 0 Fast back-to-back not supported Reset to 0
17
SERR_L Enable
RW
18
ISA Enable
RW
19
VGA Enable
RW
20
VGA 16-bit Decode
RW
21
Master Abort Mode
RW
22
Secondary Interface Reset
RW
23
Fast Back-to-Back Enable
RO
Page 41 of 145 Pericom Semiconductor November 2007, Revision 2.4
PI7C9X110
PCIe-to-PCI Reversible Bridge
BIT 24
FUNCTION Primary Master Timeout
TYPE RW
DESCRIPTION 0: Primary discard timer counts 215 PCI clock cycles 1: Primary discard timer counts 210 PCI clock cycles FORWARD BRIDGE - Bit is RO and ignored by the PI7C9X110 Reset to 0 0: Secondary discard timer counts 215 PCI clock cycles 1: Secondary discard timer counts 210 PCI clock cycles REVERSE BRIDGE - Bit is RO and ignored by PI7C9X110 Reset to 0 Bit is set when the discard timer expires and a delayed completion is discarded at the PCI interface for the forward or reverse bridge Reset to 0 Bit is set to enable to generate ERR_NONFATAL or ERR_FATAL for forward bridge, or assert P_SERR_L for reverse bridge as a result of the expiration of the discard timer on the PCI interface. Reset to 0 Reset to 0000
25
Secondary Master Timeout
RW
26
Master Timeout Status
RWC
27
Discard Timer SERR_L Enable
RW
31:28
Reserved
RO
7.4.31 PCI DATA BUFFERING CONTROL REGISTER - OFFSET 40h
BIT 0 FUNCTION Secondary Internal Arbiter's PARK Function TYPE RW DESCRIPTION 0: Park to the last master 1: Park to PI7C9X110 secondary port Reset to 0 0: Enable memory read prefetching dynamic control for PCI to PCIe read 1: Disable memory read prefetching dynamic control for PCI to PCIe read Reset to 0 0: Enable completion data prediction for PCI to PCIe read. 1: Disable completion data prediction Reset to 0 Reset to 0 These two bits are ignored in PCI-X mode. 00: One cache line prefetch if memory read multiple address is in prefetchable range at the PCI interface 01: Full prefetch if address is in prefetchable range at PCI interface, and the PI7C9X110 will keep remaining data after it disconnects the external master during burst read with read multiple command until the discard timer expires 10: Full prefetch if address is in prefetchable range at PCI interface 11: Full prefetch if address is in prefetchable range at PCI interface and the PI7C9X110 will keep remaining data after the read multiple is terminated either by an external master or by the PI7C9X110, until the discard time expires Reset to 10
1
Memory Read Prefetching Dynamic Control Disable
RW
2
Completion Data Prediction Control
RW
3 5:4
Reserved PCI Read Multiple Prefetch Mode
RO RW
Page 42 of 145 Pericom Semiconductor November 2007, Revision 2.4
PI7C9X110
PCIe-to-PCI Reversible Bridge
BIT 7:6
FUNCTION PCI Read Line Prefetch Mode
TYPE RW
DESCRIPTION These two bits are ignored in PCI-X mode. 00: Once cache line prefetch if memory read address is in prefetchable range at PCI interface 01: Full prefetch if address is in prefetchable range at PCI interface and the PI7C9X110 will keep remaining data after it is disconnected by an external master during burst read with read line command, until discard timer expires 10: Full prefetch if memory read line address is in prefetchable range at PCI interface 11: Full prefetch if address is in prefetchable range at PCI interface and the PI7C9X110 will keep remaining data after the read line is terminated either by an external master or by the PI7C9X110, until the discard timer expires Reset to 00 00: One cache line prefetch if memory read address is in prefetchable range at PCI interface 01: Reserved 10: Full prefetch if memory read address is in prefetchable range at PCI interface 11: Disconnect on the first DWORD Reset to 00 0: Retry any master at PCI bus that repeats its transaction with command code changes. 1: Allows any master at PCI bus to change memory command code (MR, MRL, MRM) after it has received a retry. The PI7C9X110 will complete the memory read transaction and return data back to the master if the address and byte enables are the same. Reset to 0 Reset to 0 Maximum byte count is used by the PI7C9X110 when generating memory read requests on the PCIe link in response to a memory read initiated on the PCI bus and bit [9:8], bit [7:6], and bit [5:4] are set to "full prefetch". 000: 001: 010: 011: 100: 101: 110: 111: 512 bytes (default) 128 bytes 256 bytes 512 bytes 1024 bytes 2048 bytes 4096 bytes 512 bytes
9:8
PCI Read Prefetch Mode
RW
10
PCI Special Delayed Read Mode Enable
RW
11 14:12
Reserved Maximum Memory Read Byte Count
RO RW
Reset to 000
7.4.32 CHIP CONTROL 0 REGISTER - OFFSET 40h
BIT 15 FUNCTION Flow Control Update Control TYPE RW DESCRIPTION 0: Flow control is updated for every two credits available 1: Flow control is updated for every on credit available Reset to 0
Page 43 of 145 Pericom Semiconductor November 2007, Revision 2.4
PI7C9X110
PCIe-to-PCI Reversible Bridge
BIT 16
FUNCTION PCI Retry Counter Status
TYPE RWC
DESCRIPTION 0: The PCI retry counter has not expired since the last reset 1: The PCI retry counter has expired since the last reset Reset to 0 00: No expiration limit 01: Allow 256 retries before expiration 10: Allow 64K retries before expiration 11: Allow 2G retries before expiration Reset to 00 0: Enable the PCI discard timer in conjunction with bit [27] offset 3Ch (bridge control register) 1: Disable the PCI discard timer in conjunction with bit [27] offset 3Ch (bridge control register) Reset to 0 0: Use bit [24] offset 3Ch for forward bridge or bit [25] offset 3Ch for reverse bridge to indicate how many PCI clocks should be allowed before the PCI discard timer expires 1: 64 PCI clocks allowed before the PCI discard timer expires Reset to 0 00: Timer expires at 25us 01: Timer expires at 0.5ms 10: Timer expires at 5ms 11: Timer expires at 25ms Reset to 01 0: Enable out-of-order capability between delayed transactions 1: Disable out-of-order capability between delayed transactions Reset to 0 00: Timer expires at 50us 01: Timer expires at 10ms 10: Timer expires at 50ms 11: Timer disabled Reset to 01 0: All memory transactions from PCI-X to PCIe will be mapped to TC0 1: All memory transactions from PCI-X to PCIe will be mapped to Traffic Class defined in bit [29:27] of offset 40h. Reset to 0 Reset to 001 0: Normal mode 1: Enable serial link interface loopback mode (TX to RX) if TM0=LOW, TM1=HIGH, TM2=HIGH, MSK_IN=HIGH, REVRSB=HIGH. PCI transaction from PCI bus will loop back to PCI bus RO for forward bridge Reset to 0 0: PI7C9X110 configuration space can be accessed from both interfaces 1: PI7C9X110 configuration space can only be accessed from the secondary interface. Primary bus accessed receives completion with CRS status for forward bridge, or target retry for reverse bridge Reset to 0 if TM0 is LOW
18:17
PCI Retry Counter Control
RW
19
PCI Discard Timer Disable
RW
20
PCI Discard Timer Short Duration
RW
22:21
Configuration Request Retry Timer Counter Value Control
RW
23
Delayed Transaction Order Control
RW
25:24
Completion Timer Counter Value Control
RW
26
Isochronous Traffic Support Enable
RW
29:27 30
Traffic Class Used For Isochronous Traffic Serial Link Interface Loopback Enable
RW RW / RO
31
Primary Configuration Access Lockout
RO / RW
Page 44 of 145 Pericom Semiconductor November 2007, Revision 2.4
PI7C9X110
PCIe-to-PCI Reversible Bridge
Page 45 of 145 Pericom Semiconductor November 2007, Revision 2.4
PI7C9X110
PCIe-to-PCI Reversible Bridge
7.4.33 RESERVED REGISTER - OFFSET 44h
BIT 31:0 FUNCTION Reserved TYPE RO DESCRIPTION Reset to 00000000h
7.4.34 ARBITER ENABLE REGISTER - OFFSET 48h
BIT 0 FUNCTION Enable Arbiter 0 TYPE RW DESCRIPTION 0: Disable arbitration for internal PI7C9X110 request 1: Enable arbitration for internal PI7C9X110 request Reset to 1 0: Disable arbitration for master 1 1: Enable arbitration for master 1 Reset to 1 0: Disable arbitration for master 2 1: Enable arbitration for master 2 Reset to 1 0: Disable arbitration for master 3 1: Enable arbitration for master 3 Reset to 1 0: Disable arbitration for master 4 1: Enable arbitration for master 4 Reset to 1 0: Disable arbitration for master 5 1: Enable arbitration for master 5 Reset to 1 0: Disable arbitration for master 6 1: Enable arbitration for master 6 Reset to 1 0: Disable arbitration for master 7 1: Enable arbitration for master 7 Reset to 1 0: Disable arbitration for master 8 1: Enable arbitration for master 8 Reset to 1
1
Enable Arbiter 1
RW
2
Enable Arbiter 2
RW
3
Enable Arbiter 3
RW
4
Enable Arbiter 4
RW
5
Enable Arbiter 5
RW
6
Enable Arbiter 6
RW
7
Enable Arbiter 7
RW
8
Enable Arbiter 8
RW
7.4.35 ARBITER MODE REGISTER - OFFSET 48h
BIT 9 FUNCTION External Arbiter Bit TYPE RO DESCRIPTION 0: Enable internal arbiter (if CFN_L is tied LOW) 1: Use external arbiter (if CFN_L is tied HIGH) Reset to 0/1 according to what CFN_L is tied to 0: Broken master timeout disable 1: This bit enables the internal arbiter to count 16 PCI bus cycles while waiting for FRAME_L to become active when a device's PCI bus GNT is active and the PCI bus is idle. If the broken master timeout expires, the PCI bus GNT for the device is de-asserted. Reset to 0
10
Broken Master Timeout Enable
RW
Page 46 of 145 Pericom Semiconductor November 2007, Revision 2.4
PI7C9X110
PCIe-to-PCI Reversible Bridge
BIT 11
FUNCTION Broken Master Refresh Enable
TYPE RW
DESCRIPTION 0: A broken master will be ignored forever after de-asserting its REQ_L for at least 1 clock 1: Refresh broken master state after all the other masters have been served once Reset to 0 08h: These bits are the initialization value of a counter used by the internal arbiter. It controls the number of PCI bus cycles that the arbiter holds a device's PCI bus GNT active after detecting a PCI bus REQ_L from another device. The counter is reloaded whenever a new PCI bus GNT is asserted. For every new PCI bus GNT, the counter is armed to decrement when it detects the new fall of FRAME_L. If the arbiter fairness counter is set to 00h, the arbiter will not remove a device's PCI bus GNT until the device has deasserted its PCI bus REQ. Reset to 08h 0: GNT_L not de-asserted after granted master assert FRAME_L 1: GNT_L de-asserts for 1 clock after 2 clocks of the granted master asserting FRAME_L Reset to 0 Reset to 0
19:12
Arbiter Fairness Counter
RW
20
GNT_L Output Toggling Enable
RW
21
Reserved
RO
7.4.36 ARBITER PRIORITY REGISTER - OFFSET 48h
BIT 22 FUNCTION Arbiter Priority 0 TYPE RW DESCRIPTION 0: Low priority request to internal PI7C9X110 1: High priority request to internal PI7C9X110 Reset to 1 0: Low priority request to master 1 1: High priority request to master 1 Reset to 0 0: Low priority request to master 2 1: High priority request to master 2 Reset to 0 0: Low priority request to master 3 1: High priority request to master 3 Reset to 0 0: Low priority request to master 4 1: High priority request to master 4 Reset to 0 0: Low priority request to master 5 1: High priority request to master 5 Reset to 0 0: Low priority request to master 6 1: High priority request to master 6 Reset to 0 0: Low priority request to master 7 1: High priority request to master 7 Reset to 0
23
Arbiter Priority 1
RW
24
Arbiter Priority 2
RW
25
Arbiter Priority 3
RW
26
Arbiter Priority 4
RW
27
Arbiter Priority 5
RW
28
Arbiter Priority 6
RW
29
Arbiter Priority 7
RW
Page 47 of 145 Pericom Semiconductor November 2007, Revision 2.4
PI7C9X110
PCIe-to-PCI Reversible Bridge
BIT 30
FUNCTION Arbiter Priority 8
TYPE RW
DESCRIPTION 0: Low priority request to master 8 1: High priority request to master 8 Reset to 0 Reset to 0
31
Reserved
RO
7.4.37 RESERVED REGISTERS - OFFSET 4Ch - 64h 7.4.38 EXPRESS TRANSMITTER/RECEIVER REGISTER - OFFSET 68h
BIT 1:0 FUNCTION Nominal Driver Current Control TYPE RW DESCRIPTION 00: 20mA 01: 10mA 10: 28mA 11: Reserved Reset to 00 0000: 1.00 x nominal driver current 0001: 1.05 x nominal driver current 0010: 1.10 x nominal driver current 0011: 1.15 x nominal driver current 0100: 1.20 x nominal driver current 0101: 1.25 x nominal driver current 0110: 1.30 x nominal driver current 0111: 1.35 x nominal driver current 1000: 1.60 x nominal driver current 1001: 1.65 x nominal driver current 1010: 1.70 x nominal driver current 1011: 1.75 x nominal driver current 1100: 1.80 x nominal driver current 1101: 1.85 x nominal driver current 1110: 1.90 x nominal driver current 1111: 1.95 x nominal driver current Reset to 0000 0000: 0.00 db 0001: -0.35 db 0010: -0.72 db 0011: -1.11 db 0100: -1.51 db 0101: -1.94 db 0110: -2.38 db 0111: -2.85 db 1000: -3.35 db 1001: -3.88 db 1010: -4.44 db 1011: -5.04 db 1100: -5.68 db 1101: -6.38 db 1110: -7.13 db 1111: -7.96 db Reset to 1000 00: 52 ohms 01: 57 ohms 10: 43 ohms 11: 46 ohms Reset to 00
5:2
Driver Current Scale Multiple Control
RW
11:8
Driver De-emphasis Level Control
RW
13:12
Transmitter Termination Control
RW
Page 48 of 145 Pericom Semiconductor November 2007, Revision 2.4
PI7C9X110
PCIe-to-PCI Reversible Bridge
BIT 15:14
FUNCTION Receiver Termination Control
TYPE RW
DESCRIPTION 00: 52 ohms 01: 57 ohms 10: 43 ohms 11: 46 ohms Reset to 00 Reset to 00h
29:16
Reserved
RO
7.4.39 UPSTREAM MEMORY WRITE FRAGMENT CONTROL REGISTER - OFFSET 68h
BIT 31:30 FUNCTION Memory Write Fragment Control TYPE RW DESCRIPTION Upstream Memory Write Fragment Control 00: Fragment at 32-byte boundary 01: Fragment at 64-byte boundary 1x: Fragement at 128-byte boundary Reset to 10h
7.4.40 RESERVED REGISTER - OFFSET 6Ch 7.4.41 EEPROM AUTOLOAD CONTROL/STATUS REGISTER - OFFSET 70h
BIT 0 FUNCTION Initiate EEPROM Read or Write Cycle TYPE RW DESCRIPTION This bit will be reset to 0 after the EEPROM operation is finished. 0: EEPROM AUTOLOAD disabled 0 -> 1: Starts the EEPROM Read or Write cycle Reset to 0 0: Read 1: Write Reset to 0 0: EEPROM acknowledge is always received during the EEPROM cycle 1: EEPROM acknowledge is not received during EEPROM cycle Reset to 0 0: EEPROM autoload is not successfully completed 1: EEPROM autoload is successfully completed Reset to 0 Where PCLK is 125MHz 00: PCLK / 4096 01: PCLK / 2048 10: PCLK / 1024 11: PCLK / 128 Reset to 00 0: Enable EEPROM autoload 1: Disable EEPROM autoload Reset to 0 0: Normal speed of EEPROM autoload 1: Increase EEPROM autoload by 32x Reset to 0
1
Control Command for EEPROM
RW
2
EEPROM Error
RO
3
EPROM Autoload Complete Status
RO
5:4
EEPROM Clock Frequency Control
RW
6
EEPROM Autoload Control
RW
7
Fast EEPROM Autoload Control
RW
Page 49 of 145 Pericom Semiconductor November 2007, Revision 2.4
PI7C9X110
PCIe-to-PCI Reversible Bridge
BIT 8
FUNCTION EEPROM Autoload Status
TYPE RO
DESCRIPTION 0: EEPROM autoload is not on going 1: EEPROM autoload is on going Reset to 0 EEPROM word address for EEPROM cycle Reset to 0000000 EEPROM data to be written into the EEPROM Reset to 0000h
15:9
EEPROM Word Address
RW
31:16
EEPROM Data
RW
Page 50 of 145 Pericom Semiconductor November 2007, Revision 2.4
PI7C9X110
PCIe-to-PCI Reversible Bridge
7.4.42 RESERVED REGISTER - OFFSET 74h 7.4.43 GPIO DATA AND CONTROL REGISTER - OFFSET 78h
BIT 11:0 15:12 19:16 23:20 27:24 31:28 FUNCTION Reserved GPIO Output Write-1-toClear GPIO Output Write-1-to-Set GPIO Output Enable Write1-to-Clear GPIO Output Enable Write1-to-Set GPIO Input Data Register TYPE RO RW RW RW RW RO DESCRIPTION Reset to 000h Reset to 0h Reset to 0h Reset to 0h Reset to 0h Reset to 0h
7.4.44 RESERVED REGISTER - OFFSET 7Ch 7.4.45 PCI-X CAPABILITY ID REGISTER - OFFSET 80h
BIT 7:0 FUNCTION PCI-X Capability ID TYPE RO DESCRIPTION PCI-X Capability ID Reset to 07h
7.4.46 NEXT CAPABILITY POINTER REGISTER - OFFSET 80h
BIT 15:8 FUNCTION Next Capability Pointer TYPE RO DESCRIPTION Point to power management Reset to 90h
7.4.47 PCI-X SECONDARY STATUS REGISTER - OFFSET 80h
BIT 16 FUNCTION 64-bit Device on Secondary Bus Interface 133MHz Capable TYPE RO DESCRIPTION 64-bit not supported Reset to 0 When this bit is 1, PI7C9X110 is 133MHz capable on its secondary bus interface Reset to 1 in forward bridge mode or 0 in reverse bridge mode This bit is a read-only and set to 0 in reverse bridge mode or is read-write in forward bridge mode When this is set to 1, a split completion has been discarded by PI7C9X110 at secondary bus because the requester did not accept the split completion transaction Reset to 0 This bit is set to 0 in forward bridge mode or is read-write in reverse bridge mode When this is set to 1, an unexpected split completion has been received with the requester ID equaled to the secondary bus number, device number, and function number at the PI7X9X110 secondary bus interface Reset to 0
17
RO
18
Split Completion Discarded
RO / RWC
19
Unexpected Split Completion
RWC
Page 51 of 145 Pericom Semiconductor November 2007, Revision 2.4
PI7C9X110
PCIe-to-PCI Reversible Bridge
BIT 20
FUNCTION Split Completion Overrun
TYPE RWC
DESCRIPTION When this bit is set to 1, a split completion has been terminated by PI7C9X110 with either a retry or disconnect at the next ADB due to the buffer full condition Reset to 0 When this bit is set to 1, a split request is delayed because PI7C9X110 is not able to forward the split request transaction to its secondary bus due to insufficient room within the limit specified in the split transaction commitment limit field of the downstream split transaction control register Reset to 0 These bits are only meaningful in forward bridge mode. In reverse bridge mode, all three bits are set to zero. 000: Conventional PCI mode (minimum clock period not applicable) 001: 66MHz (minimum clock period is 15ns) 010: 100 to 133MHz (minimum clock period is 7.5ns) 011: Reserved 1xx: Reserved Reset to 000 0000000
21
Split Request Delayed
RWC
24:22
Secondary Clock Frequency
RO
31:25
Reserved
RO
7.4.48 PCI-X BRIDGE STATUS REGISTER - OFFSET 84h
BIT 2:0 FUNCTION Function Number TYPE RO DESCRIPTION Function number (AD [10:8] of a type 0 configuration transaction) Reset to 000 Device number (AD [15:11] of a type 0 configuration transaction) is assigned to the PI7C9X110 by the connection of system hardware. Each time the PI7C9X110 is addressed by a configuration write transaction, the bridge updates this register with the contents of AD [15:11] of the address phase of the configuration transaction, regardless of which register in the PI7C9X110 is addressed by the transaction. The PI7C9X110 is addressed by a configuration write transaction if all of the following are true: * The transaction uses a configuration write command * IDSEL is asserted during the address phase * AD [1:0] are 00 (type o configuration transaction) * AD [10:8] of the configuration address contain the appropriate function number Reset to 11111 Additional address from which the contents of the primary bus number register on type 1 configuration space header is read. The PI7C9X110 uses the bus number, device number, and function number fields to create a completer ID when responding with a split completion to a read of an internal PI7C9X110 register. These fields are also used for cases when one interface is in conventional PCI mode and the other is in PCI-X mode. Reset to 11111111 64-bit not supported Reset to 0 When this bit is 1, PI7C9X110 is 133MHz capable on its primary bus interface Reset to 0 in forward bridge mode or 1 in reverse bridge mode
7:3
Device Number
RO
15:8
Bus Number
RO
16
64-bit Device on Primary Bus Interface 133MHz Capable
RO
17
RO
Page 52 of 145 Pericom Semiconductor November 2007, Revision 2.4
PI7C9X110
PCIe-to-PCI Reversible Bridge
BIT 18
FUNCTION Split Completion Discarded
TYPE RO / RWC
DESCRIPTION This bit is a read-only and set to 0 in reverse bridge mode or is read-write in forward bridge mode When this is set to 1, a split completion has been discarded by PI7C9X110 at primary bus because the requester did not accept the split completion transaction Reset to 0 This bit is set to 0 in forward bridge mode or is read-write in reverse bridge mode When this is set to 1, an unexpected split completion has been received with the requester ID equaled to the primary bus number, device number, and function number at the PI7X9X110 primary bus interface Reset to 0 When this bit is set to 1, a split completion has been terminated by PI7C9X110 with either a retry or disconnect at the next ADB due to the buffer full condition Reset to 0 When this bit is set to 1, a split request is delayed because PI7C9X110 is not able to forward the split request transaction to its primary bus due to insufficient room within the limit specified in the split transaction commitment limit field of the downstream split transaction control register Reset to 0 0000000000
19
Unexpected Split Completion
RWC
20
Split Completion Overrun
RWC
21
Split Request Delayed
RWC
31:22
Reserved
RO
7.4.49 UPSTREAM SPLIT TRANSACTION REGISTER - OFFSET 88h
BIT 15:0 FUNCTION Upstream Split Transaction Capability TYPE RO DESCRIPTION Upstream Split Transaction Capability specifies the size of the buffer (in the unit of ADQs) to store split completions for memory read. It applies to the requesters on the secondary bus in addressing the completers on the primary bus. The 0010h value shows that the buffer has 16 ADQs or 2K bytes storage Reset to 0010h Upstream Split Transaction Commitment Limit indicates the cumulative sequence size of the commitment limit in units of ADQs. This field can be programmed to any value or equal to the content of the split capability field. For example, if the limit is set to FFFFh, PI7C9X110 is allowed to forward all split requests of any size regardless of the amount of buffer space available. The split transaction commitment limit is set to 0010h that is the same value as the split transaction capability. Reset to 0010h
31:16
Upstream Split Transaction Commitment Limit
RW
7.4.50 DOWNSTREAM SPLIT TRANSACTION REGISTER - OFFSET 8Ch
BIT 15:0 FUNCTION Downstream Split Transaction Capability TYPE RO DESCRIPTION Downstream Split Transaction Capability specifies the size of the buffer (in the unit of ADQs) to store split completions for memory read. It applies to the requesters on the primary bus in addressing the completers on the secondary bus. The 0010h value shows that the buffer has 16 ADQs or 2K bytes storage Reset to 0010h
Page 53 of 145 Pericom Semiconductor November 2007, Revision 2.4
PI7C9X110
PCIe-to-PCI Reversible Bridge
BIT 31:16
FUNCTION Downstream Split Transaction Commitment Limit
TYPE RW
DESCRIPTION Downstream Split Transaction Commitment Limit indicates the cumulative sequence size of the commitment limit in units of ADQs. This field can be programmed to any value or equal to the content of the split capability field. For example, if the limit is set to FFFFh, PI7C9X110 is allowed to forward all split requests of any size regardless of the amount of buffer space available. The split transaction commitment limit is set to 0010h that is the same value as the split transaction capability. Reset to 0010h
7.4.51 POWER MANAGEMENT ID REGISTER - OFFSET 90h
BIT 7:0 FUNCTION Power Management ID TYPE RO DESCRIPTION Power Management ID Register Reset to 01h
7.4.52 NEXT CAPABILITY POINTER REGISTER - OFFSET 90h
BIT 15:8 FUNCTION Next Pointer TYPE RO DESCRIPTION Next pointer (point to Subsystem ID and Subsystem Vendor ID) Reset to A8h
7.4.53 POWER MANAGEMENT CAPABILITY REGISTER - OFFSET 90h
BIT 18:16 FUNCTION Version Number TYPE RO DESCRIPTION Version number that complies with revision 2.0 of the PCI Power Management Interface specification. Reset to 010 PME clock is not required for PME_L generation Reset to 0 Reset to 0 DSI - no special initialization of this function beyond the standard PCI configuration header is required following transition to the D0 un-initialized state Reset to 0 000: 0mA 001: 55mA 010: 100mA 011: 160mA 100: 220mA 101: 270mA 110: 320mA 111: 375mA Reset to 001 D1 power management is not supported Reset to 0 D2 power management is not supported Reset to 0 PME_L is supported in D3 cold, D3 hot, and D0 states. Reset to 11001
19
PME Clock
RO
20 21
Reserved Device Specific Initialization (DSI)
RO RO
24:22
AUX Current
RO
25
D1 Power Management
RO
26
D2 Power Management
RO
31:27
PME_L Support
RO
Page 54 of 145 Pericom Semiconductor November 2007, Revision 2.4
PI7C9X110
PCIe-to-PCI Reversible Bridge
7.4.54 POWER MANAGEMENT CONTROL AND STATUS REGISTER - OFFSET 94h
BIT 1:0 FUNCTION Power State TYPE RW DESCRIPTION Power State is used to determine the current power state of PI7C9X110. If a non-implemented state is written to this register, PI7C9X110 will ignore the write data. When present state is D3 and changing to D0 state by programming this register, the power state change causes a device reset without activating the RESET_L of PCI/PCI-X bus interface 00: D0 state 01: D1 state not implemented 10: D2 state not implemented 11: D3 state Reset to 00 Reset to 000000 0: PME_L assertion is disabled 1: PME_L assertion is enabled Reset to 0 Data register is not implemented Reset to 0000 Data register is not implemented Reset to 00 PME_L is supported Reset to 0
7:2 8
Reserved PME Enable
RO RWS
12:9
Data Select
RO
14:13
Data Scale
RO
15
PME Status
RWCS
7.4.55 PCI-TO-PCI SUPPORT EXTENSION REGISTER - OFFSET 94h
BIT 21:16 22 FUNCTION Reserved B2/B3 Support TYPE RO RO DESCRIPTION Reset to 000000 0: B2 / B3 not support for D3hot Reset to 0 0: PCI Bus Power/Clock Disabled Reset to 0 Data register is not implemented Reset to 00h
23
PCI Bus Power/Clock Control Enable Data Register
RO
31:24
RO
7.4.56 RESERVED REGISTERS - OFFSET 98h - 9Ch 7.4.57 CAPABILITY ID REGISTER - OFFSET A0h
BIT 7:0 FUNCTION Capability ID TYPE RO DESCRIPTION Capability ID for Slot Identification. SI is off by default but can be turned on through EEPROM interface Reset to 04h
7.4.58 NEXT POINTER REGISTER - OFFSET A0h
BIT 15:8 FUNCTION Next Pointer TYPE RO DESCRIPTION Next pointer - points to PCI Express capabilities register Reset to B0h
Page 55 of 145 Pericom Semiconductor November 2007, Revision 2.4
PI7C9X110
PCIe-to-PCI Reversible Bridge
7.4.59 SLOT NUMBER REGISTER - OFFSET A0h
BIT 20:16 FUNCTION Expansion Slot Number TYPE RW DESCRIPTION Expansion slot number Reset to 00000 First in chassis Reset to 0 Reset to 00
21
First In Chassis
RW
23:22
Reserved
RO
7.4.60 CHASSIS NUMBER REGISTER - OFFSET A0h
BIT 31:24 FUNCTION Chassis Number TYPE RW DESCRIPTION Chassis number Reset to 00h
7.4.61 SECONDARY CLOCK AND CLKRUN CONTROL REGISTER - OFFSET A4h
BIT 1:0 FUNCTION S_CLKOUT0 Enable TYPE RW DESCRIPTION S_CLKOUT (Slot 0) Enable for forward bridge mode only 00: enable S_CLKOUT0 01: enable S_CLKOUT0 10: enable S_CLKOUT0 11: disable S_CLKOUT0 and driven LOW Reset to 00 S_CLKOUT (Slot 1) Enable for forward bridge mode only 00: enable S_CLKOUT1 01: enable S_CLKOUT1 10: enable S_CLKOUT1 11: disable S_CLKOUT1 and driven LOW Reset to 00 S_CLKOUT (Slot 2) Enable for forward bridge mode only 00: enable S_CLKOUT2 01: enable S_CLKOUT2 10: enable S_CLKOUT2 11: disable S_CLKOUT2 and driven LOW Reset to 00 S_CLKOUT (Slot 3) Enable for forward bridge mode only 00: enable S_CLKOUT3 01: enable S_CLKOUT3 10: enable S_CLKOUT3 11: disable S_CLKOUT3 and driven LOW Reset to 00 S_CLKOUT (Device 1) Enable for forward bridge mode only 0: enable S_CLKOUT4 1: disable S_CLKOUT4 and driven LOW Reset to 0
3:2
S_CLKOUT1 Enable
RW
5:4
S_CLKOUT2 Enable
RW
7:6
S_CLKOUT3 Enable
RW
8
S_CLKOUT4 Enable
RW
Page 56 of 145 Pericom Semiconductor November 2007, Revision 2.4
PI7C9X110
PCIe-to-PCI Reversible Bridge
BIT 9
FUNCTION S_CLKOUT5 Enable
TYPE RW
DESCRIPTION S_CLKOUT (Device 2) Enable for forward bridge mode only 0: enable S_CLKOUT5 1: disable S_CLKOUT5 and driven LOW Reset to 0 S_CLKOUT (Device 3) Enable for forward bridge mode only 0: enable S_CLKOUT6 1: disable S_CLKOUT6 and driven LOW Reset to 0 S_CLKOUT (Device 4) Enable for forward bridge mode only 0: enable S_CLKOUT7 1: disable S_CLKOUT7 and driven LOW Reset to 0 S_CLKOUT (the bridge) Enable for forward bridge mode only 0: enable S_CLKOUT8 1: disable S_CLKOUT8 and driven LOW Reset to 0 Secondary clock stop status 0: secondary clock not stopped 1: secondary clock stopped Reset to 0 0: disable protocol 1: enable protocol Reset to 0 0: Stop the secondary clock only when bridge is at D3hot state 1: Stop the secondary clock whenever the secondary bus is idle and there are no requests from the primary bus Reset to 0 Reset to 0000h
10
S_CLKOUT6 Enable
RW
11
S_CLKOUT7 Enable
RW
12
S_CLKOUT8 Enable
RW
13
Secondary Clock Stop Status
RO
14
Secondary Clkrun Protocol Enable
RW
15
Clkrun Mode
RW
31:16
Reserved
RO
7.4.62 CAPABILITY ID REGISTER - OFFSET A8h
BIT 7:0 FUNCTION Capability ID TYPE RO DESCRIPTION Capability ID for subsystem ID and subsystem vendor ID Reset to 0Dh
7.4.63 NEXT POINTER REGISTER - OFFSET A8h
BIT 15:8 FUNCTION Next Item Pointer TYPE RO DESCRIPTION Next item pointer (point to PCI Express Capability by default but can be programmed to A0h if Slot Identification Capability is enabled) Reset to B0h
7.4.64 RESERVED REGISTER - OFFSET A8h
BIT 31:16 FUNCTION Reserved TYPE RO DESCRIPTION Reset to 0000h
Page 57 of 145 Pericom Semiconductor November 2007, Revision 2.4
PI7C9X110
PCIe-to-PCI Reversible Bridge
7.4.65 SUBSYSTEM VENDOR ID REGISTER - OFFSET ACh
BIT 15:0 FUNCTION Subsystem Vendor ID TYPE RO DESCRIPTION Subsystem vendor ID identifies the particular add-in card or subsystem Reset to 00h
7.4.66 SUBSYSTEM ID REGISTER - OFFSET ACh
BIT 31:16 FUNCTION Subsystem ID TYPE RO DESCRIPTION Subsystem ID identifies the particular add-in card or subsystem Reset to 00h
7.4.67 PCI EXPRESS CAPABILITY ID REGISTER - OFFSET B0h
BIT 7:0 FUNCTION PCI Express Capability ID TYPE RO DESCRIPTION PCI Express capability ID Reset to 10h
7.4.68 NEXT CAPABILITY POINTER REGISTER - OFFSET B0h
BIT 15:8 FUNCTION Next Item Pointer TYPE RO DESCRIPTION Next item pointer (points to VPD register) Reset to D8h
7.4.69 PCI EXPRESS CAPABILITY REGISTER - OFFSET B0h
BIT 19:16 23:20 FUNCTION Capability Version Device / Port Type TYPE RO RO DESCRIPTION Reset to 1h 0000: PCI Express endpoint device 0001: Legacy PCI Express endpoint device 0100: Root port of PCI Express root complex 0101: Upstream port of PCI Express switch 0110: Downstream port of PCI Express switch 0111: PCI Express to PCI bridge 1000: PCI to PCI Express bridge Others: Reserved Reset to 7h for Forward Bridge or 8h for Reverse Bridge Reset to 0 for Forward Bridge or 1 for Reverse Bridge Reset to 0h Reset to 0
24 29:25 31:30
Slot Implemented Interrupt Message Number Reserved
RO RO RO
7.4.70 DEVICE CAPABILITY REGISTER - OFFSET B4h
BIT 2:0 FUNCTION Maximum Payload Size TYPE RO DESCRIPTION 000: 128 bytes 001: 256 bytes 010: 512 bytes 011: 1024 bytes 100: 2048 bytes 101: 4096 bytes 110: reserved 111: reserved Reset to 001
Page 58 of 145 Pericom Semiconductor November 2007, Revision 2.4
PI7C9X110
PCIe-to-PCI Reversible Bridge
BIT 4:3
FUNCTION Phantom Functions
TYPE RO
DESCRIPTION No phantom functions supported Reset to 00 8-bit tag field supported Reset to 1 Endpoint L0's acceptable latency 000: less than 64 ns 001: 64 - 128 ns 010: 128 - 256 ns 011: 256 - 512 ns 100: 512 ns - 1 us 101: 1 - 2 us 110: 2 - 4 us 111: more than 4 us Reset to 000 Endpoint L1's acceptable latency 000: less than 1 us 001: 1 - 2 us 010: 2 - 4 us 011: 4 - 8 us 100: 8 - 16 us 101: 16 - 32 us 110: 32 - 64 us 111: more than 64 us Reset to 000 0: If Hot Plug is disabled 1: If Hot Plug is enabled at Forward Bridge Reset to 0 when hot-plug is disabled or 1 when hot-plug is enabled through strapping. 0: If Hot Plug is disabled 1: If Hot Plug is enable at Forward Bridge Reset to 0 when hot-plug is disabled or 1 when hot-plug is enabled through strapping. 0: If Hot Plug is disabled 1: If Hot Plug is enable at Forward Bridge Reset to 0 when hot-plug is disabled or 1 when hot-plug is enabled through strapping. Reset to 000 These bits are set by the Set_Slot_Power_Limit message Reset to 00h This value is set by the Set_Slot_Power_Limit message Reset to 00 Reset to 0h
5
8-bit Tag Field
RO
8:6
Endpoint L0's Latency
RO
11:9
Endpoint L1's Latency
RO
12
Attention Button Present
RO
13
Attention Indicator Present
RO
14
Power Indicator Present
RO
17:15 25:18
Reserved Captured Slot Power Limit Value Captured Slot Power Limit Scale Reserved
RO RO
27:26
RO
31:28
RO
7.4.71 DEVICE CONTROL REGISTER - OFFSET B8h
BIT 0 1 2 FUNCTION Correctable Error Reporting Enable Non-Fatal Error Reporting Enable Fatal Error Reporting Enable TYPE RW RW RW DESCRIPTION Reset to 0h Reset to 0h Reset to 0h
Page 59 of 145 Pericom Semiconductor November 2007, Revision 2.4
PI7C9X110
PCIe-to-PCI Reversible Bridge
BIT 3 4 7:5
FUNCTION Unsupported Request Reporting Enable Relaxed Ordering Enable Max Payload Size
TYPE RW RO RW
DESCRIPTION Reset to 0h Relaxed Ordering disabled Reset to 0h This field sets the maximum TLP payload size for the PI7C9X110 000: 128 bytes 001: 256 bytes 010: 512 bytes 011:1024 bytes 100: 2048 bytes 101: 4096 bytes 110: reserved 111: reserved Reset to 000 Reset to 0 Phantom functions not supported Reset to 0 Auxiliary power PM not supported Reset to 0 Bridge never sets the No Snoop attribute in the transaction it initiates Reset to 0 This field sets the maximum Read Request Size for the device as a requester 000: 128 bytes 001: 256 bytes 010: 512 bytes 011: 1024 bytes 100: 2048 bytes 101: 4096 bytes 110: reserved 111: reserved Reset to 2h Reset to 0
8 9
Extended Tag Field Enable Phantom Functions Enable
RW RO
10
Auxiliary Power PM Enable
RO
11
No Snoop Enable
RO
14:12
Maximum Read Request Size
RW
15
Configuration Retry Enable
RW
7.4.72 DEVICE STATUS REGISTER - OFFSET B8h
BIT 16 17 18 19 20 21 FUNCTION Correctable Error Detected Non-Fatal Error Detected Fatal Error Detected Unsupported Request Detected AUX Power Detected Transaction Pending TYPE RWC RWC RWC RWC RO RO DESCRIPTION Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 1 0: No transaction is pending on transaction layer interface 1: Transaction is pending on transaction layer interface Reset to 0 Reset to 0000000000
31:22
Reserved
RO
7.4.73 LINK CAPABILITY REGISTER - OFFSET BCh
BIT FUNCTION TYPE DESCRIPTION
Page 60 of 145 Pericom Semiconductor November 2007, Revision 2.4
PI7C9X110
PCIe-to-PCI Reversible Bridge
BIT 3:0
FUNCTION Maximum Link Speed
TYPE RO
DESCRIPTION Indicates the maximum speed of the Express link 0001: 2.5Gb/s link Reset to 1 Indicates the maximum width of the Express link (x1 at reset) 000000: reserved 000001: x1 000010: x2 000100: x4 001000: x8 001100: x12 010000: x16 100000: x32 Reset to 000001 This field indicates the level of Active State Power Management Support 00: reserved 01: L0's entry supported 10: reserved 11: L0's and L1's supported Reset to 11 Reset to 3h Reset to 0h Reset to 0h Reset to 00h
9:4
Maximum Link Width
RO
11:10
ASPM Support
RO
14:12 17:15 23:18 31:24
L0's Exit Latency L1's Exit Latency Reserved Port Number
RO RO RO RO
7.4.74 LINK CONTROL REGISTER - OFFSET C0h
BIT 1:0 FUNCTION ASPM Control TYPE RW DESCRIPTION This field controls the level of ASPM supported on the Express link 00: disabled 01: L0's entry enabled 10: L1's entry enabled 11: L0's and L1's entry enabled Reset to 00 Reset to 0 Read completion boundary not supported Reset to 0 RO for Forward Bridge Reset to 0 RO for Forward Bridge Reset to 0 Reset to 0 Reset to 0 Reset to 00h
2 3
Reserved Read Completion Boundary (RCB) Link Disable
RO RO
4
RO / RW RO / RW RW RW RO
5
Retrain Link
6 7 15:8
Common Clock Configuration Extended Sync Reserved
7.4.75 LINK STATUS REGISTER - OFFSET C0h
BIT FUNCTION TYPE DESCRIPTION
Page 61 of 145 Pericom Semiconductor November 2007, Revision 2.4
PI7C9X110
PCIe-to-PCI Reversible Bridge
BIT 19:16
FUNCTION Link Speed
TYPE RO
DESCRIPTION This field indicates the negotiated speed of the Express link 001: 2.5Gb/s link Reset to 1h 000000: reserved 000001: x1 000010: x2 000100: x4 001000: x8 001100: x12 010000: x16 100000: x32 Reset to 000001 Reset to 0 Reset to 0 Reset to 1 Reset to 0
25:20
Negotiated Link Width
RO
26 27 28 31:29
Link Train Error Link Training Slot Clock Configuration Reserved
RO RO RO RO
7.4.76 SLOT CAPABILITY REGISTER - OFFSET C4h
BIT 0 FUNCTION Attention Button Present TYPE RO DESCRIPTION 0: If Hot Plug is disabled 1: If Hot Plug is enabled at reverse bridge Reset to 0 when hot-plug is disabled or 1 when hot-plug is enabled through strapping. Reset to 0 0: If Hot Plug is disabled 1: If Hot Plug is enabled at reverse bridge Reset to 0 when hot-plug is disabled or 1 when hot-plug is enabled through strapping. 0: If Hot Plug is disabled 1: If Hot Plug is enabled at reverse bridge Reset to 0 when hot-plug is disabled or 1 when hot-plug is enabled through strapping. 0: If Hot Plug is disabled 1: If Hot Plug is enabled at reverse bridge Reset to 0 when hot-plug is disabled or 1 when hot-plug is enabled through strapping. Reset to 0 0: If Hot Plug is disabled 1: If Hot Plug is enabled at reverse bridge Reset to 0 when hot-plug is disabled or 1 when hot-plug is enabled through strapping. Reset to 00h Reset to 00 Reset to 00 Reset to 0
1 2
Power Controller Present MRL Sensor Present
RO RO
3
Attention Indicator Present
RO
4
Power Indicator Present
RO
5 6
Hot Plug Surprise Hot Plug Capable
RO RO
14:7 16:15 18:17 31:19
Slot Power Limit Value Slot Power Limit Scale Reserved Physical Slot Number
RO RO RO RO
7.4.77 SLOT CONTROL REGISTER - OFFSET C8h
BIT 0 1 FUNCTION Attention Button Present Enable Power Fault Detected Enable TYPE RW RW DESCRIPTION Reset to 0 Reset to 0
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PCIe-to-PCI Reversible Bridge
BIT 2 3 4 5 7:6 9:8 10 15:11
FUNCTION MRL Sensor Changed Enable Presence Detect Changed Enable Command Completed Interrupt Enable Hot Plug Interrupt Enable Attention Indicator Control Power Indicator Control Power Controller Control Reserved
TYPE RW RW RW RW RW RW RW RO
DESCRIPTION Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0
7.4.78 SLOT STATUS REGISTER - OFFSET C8h
BIT 16 17 18 19 20 21 22 31:23 FUNCTION Attention Button Pressed Power Fault Detected MRL Sensor Changed Presence Detect Changed Command Completed MRL Sensor State Presence Detect State Reserved TYPE RO RO RO RO RO RO RO RO DESCRIPTION Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0
7.4.79 XPIP CONFIGURATION REGISTER 0 - OFFSET CCh
BIT 0 1 2 3 FUNCTION Hot Reset Enable Loopback Function Enable Cross Link Function Enable Software Direct to Configuration State when in LTSSM state Internal Selection for Debug Mode Negotiate Lane Number of Times TS1 Number Counter Reserved LTSSM Enter L1 Timer Default Value TYPE RW RW RW RW DESCRIPTION Reset to 0 Reset to 0 Reset to 0 Reset to 0
4 7:5 12:8 15:13 31:16
RW RW RW RO RW
Reset to 0 Reset to 3h Reset to 10h Reset to 0 Reset to 0400h
7.4.80 XPIP CONFIGURATION REGISTER 1 - OFFSET D0h
BIT 9:0 15:10 31:16 FUNCTION L0's Lifetime Timer Reserved L1 Lifetime Timer TYPE RW RO RW DESCRIPTION Reset to 0 Reset to 0 Reset to 0
7.4.81 XPIP CONFIGURATION REGISTER 2 - OFFSET D4h
BIT 7:0 FUNCTION CDR Recovery Time (in the number of FTS order sets) L0's Exit to L0 Latency Reserved L1 Exit to L0 Latency Reserved TYPE RW DESCRIPTION Reset to 54h A Fast Training Sequence order set composes of one K28.5 (COM) Symbol and three K28.1 Symbols. Reset to 2h Reset to 0 Reset to 19h Reset to 0
14:8 15 22:16 23
RW RO RW RO
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PCIe-to-PCI Reversible Bridge
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PCIe-to-PCI Reversible Bridge
7.4.82 HOT SWAP SWITCH DEBOUNCE COUNTER - OFFSET D4h
BIT 31:24 FUNCTION Hot Swap Debounce Counter TYPE RO / RW DESCRIPTION If Hot Swap is enabled, this counter is read-write able. This counter is read only (RO) if Hot Swap is disabled 00h: 1ms 01h: 2ms 02h: 3ms 03h: 4ms ... FFh: 256ms Reset to 0
7.4.83 CAPABILITY ID REGISTER - OFFSET D8h
BIT 7:0 FUNCTION Capability ID for VPD Register TYPE RO DESCRIPTION Reset to 03h
7.4.84 NEXT POINTER REGISTER - OFFSET D8h
BIT 15:8 FUNCTION Next Pointer TYPE RO DESCRIPTION Next pointer (F0h, points to MSI capabilities) Reset to F0h
7.4.85 VPD REGISTER - OFFSET D8h
BIT 17:16 23:18 30:24 31 FUNCTION Reserved VPD Address for Read/Write Cycle Reserved VPD Operation TYPE RO RW RO RW DESCRIPTION Reset to 0 Reset to 0 Reset to 0 0: Generate a read cycle from the EEPROM at the VPD address specified in bits [7:2] of offset D8h. This bit remains at `0' until EEPROM cycle is finished, after which the bit is then set to `1'. Data for reads is available at register ECh. 1: Generate a write cycle to the EEPROM at the VPD address specified in bits [7:2] of offset D8h. This bit remains at `1' until EEPROM cycle is finished, after which it is then cleared to `0'. Reset to 0
7.4.86 VPD DATA REGISTER - OFFSET DCh
BIT 31:0 FUNCTION VPD Data TYPE RW DESCRIPTION VPD Data (EEPROM data [address + 0x40]) The least significant byte of this register corresponds to the byte of VPD at the address specified by the VPD address register. The data read form or written to this register uses the normal PCI byte transfer capabilities. Reset to 0
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PCIe-to-PCI Reversible Bridge
7.4.87 RESERVED REGISTERS - OFFSET E0h - ECh 7.4.88 MESSAGE SIGNALED INTERRUPTS ID REGISTER - F0h
BIT 7:0 FUNCTION Capability ID for MSI Registers TYPE RO DESCRIPTION Reset to 05h
7.4.89 NEXT CAPABILITIES POINTER REGISTER - F0h
BIT 15:8 FUNCTION Next Pointer TYPE RO DESCRIPTION Next pointer (00h indicates the end of capabilities) Reset to 00h
7.4.90 MESSAGE CONTROL REGISTER - OFFSET F0h
BIT 16 FUNCTION MSI Enable TYPE RW DESCRIPTION 0: Disable MSI and default to INTx for interrupt 1: Enable MSI for interrupt service and ignore INTx interrupt pins 000: 1 message requested 001: 2 messages requested 010: 4 messages requested 011: 8 messages requested 100: 16 messages requested 101: 32 messages requested 110: reserved 111: reserved Reset to 000 000: 1 message requested 001: 2 messages requested 010: 4 messages requested 011: 8 messages requested 100: 16 messages requested 101: 32 messages requested 110: reserved 111: reserved Reset to 000 Reset to 1 Reset to 00h
19:17
Multiple Message Capable
RO
22:20
Multiple Message Enable
RW
23 31:24
64-bit Address Capable Reserved
RW RO
7.4.91 MESSAGE ADDRESS REGISTER - OFFSET F4h
BIT 1:0 31:2 FUNCTION Reserved System Specified Message Address TYPE RO RW DESCRIPTION Reset to 00 Reset to 0
7.4.92 MESSAGE UPPER ADDRESS REGISTER - OFFSET F8h
BIT 31:0 FUNCTION System Specified Message Upper Address TYPE RW DESCRIPTION Reset to 0
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PCIe-to-PCI Reversible Bridge
7.4.93 MESSAGE DATA REGISTER - OFFSET FCh
BIT 15:0 31:16 FUNCTION System Specified Message Data Reserved TYPE RW RO DESCRIPTION Reset to 0 Reset to 0
7.4.94 ADVANCE ERROR REPORTING CAPABILITY ID REGISTER - OFFSET 100h
BIT 15:0 FUNCTION Advance Error Reporting Capability ID TYPE RO DESCRIPTION Reset to 0001h
7.4.95 ADVANCE ERROR REPORTING CAPABILITY VERSION REGISTER - OFFSET 100h
BIT 19:16 FUNCTION Advance Error Reporting Capability Version TYPE RO DESCRIPTION Reset to 1h
7.4.96 NEXT CAPABILITY OFFSET REGISTER - OFFSET 100h
BIT 31:20 FUNCTION Next Capability Offset TYPE RO DESCRIPTION Next capability offset (150h points to VC capability) Reset to 150h
7.4.97 UNCORRECTABLE ERROR STATUS REGISTER - OFFSET 104h
BIT 0 3:1 4 11:5 12 13 14 15 16 17 18 19 20 31:21 FUNCTION Training Error Status Reserved Data Link Protocol Error Status Reserved Poisoned TLP Status Flow Control Protocol Error Status Completion Timeout Status Completer Abort Status Unexpected Completion Status Receiver Overflow Status Malformed TLP Status ECRC Error Status Unsupported Request Error Status Reserved TYPE RWCS RO RWCS RO RWCS RWCS RWCS RWCS RWCS RWCS RWCS RWCS RWCS RO DESCRIPTION Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0
7.4.98 UNCORRECTABLE ERROR MASK REGISTER - OFFSET 108h
BIT 0 3:1 4 11:5 12 13 FUNCTION Training Error Mast Reserved Data Link Protocol Error Mask Reserved Poisoned TLP Mask Flow Control Protocol Error Mask TYPE RWS RO RWS RO RWS RWS DESCRIPTION Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0
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PCIe-to-PCI Reversible Bridge
BIT 14 15 16 17 18 19 20 31:21
FUNCTION Completion Timeout Mask Completion Abort Mask Unexpected Completion Mask Receiver Overflow Mask Malformed TLP Mask ECRC Error Mask Unsupported Request Error Mask Reserved
TYPE RWS RWS RWS RWS RWS RWS RWS RO
DESCRIPTION Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0
7.4.99 UNCORRECTABLE ERROR SEVERITY REGISTER - OFFSET 10Ch
BIT 0 3:1 4 11:5 12 13 14 15 16 17 18 19 20 31:21 FUNCTION Training Error Severity Reserved Data Link Protocol Error Severity Reserved Poisoned TLP Severity Flow Control Protocol Error Severity Completion Timeout Severity Completer Abort Severity Unexpected Completion Severity Receiver Overflow Severity Malformed TLP Severity ECRC Error Severity Unsupported Request Error Severity Reserved TYPE RWS RO RWS RO RWS RWS RWS RWS RWS RWS RWS RWS RWS RO DESCRIPTION Reset to 1 Reset to 0 Reset to 1 Reset to 0 Reset to 0 Reset to 1 Reset to 0 Reset to 0 Reset to 0 Reset to 1 Reset to 1 Reset to 0 Reset to 0 Reset to 0
7.4.100 CORRECTABLE ERROR STATUS REGISTER - OFFSET 110h
BIT 0 5:1 6 7 8 11:9 12 31:13 FUNCTION Receiver Error Status Reserved Bad TLP Status Bad DLLP Status REPLAY_NUM Rollover Status Reserved Replay Timer Timeout Status Reserved TYPE RWCS RO RWCS RWCS RWCS RO RWCS RO DESCRIPTION Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0
7.4.101 CORRECTABLE ERROR MASK REGISTER - OFFSET 114h
BIT 0 5:1 6 7 8 11:9 12 31:13 FUNCTION Receiver Error Mask Reserved Bad TLP Mask Bad DLLP Mask REPLAY_NUM Rollover Mask Reserved Replay Timer Timeout Mask Reserved TYPE RWS RO RWS RWS RWS RO RWS RO DESCRIPTION Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0
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PCIe-to-PCI Reversible Bridge
7.4.102 ADVANCED ERROR CAPABILITIES AND CONTROL REGISTER - OFFSET 118h
BIT 4:0 5 6 7 8 31:9 FUNCTION First Error Pointer ECRC Generation Capable ECRC Generation Enable ECRC Check Capable ECRC Check Enable Reserved TYPE ROS RO RWS RO RWS RO DESCRIPTION Reset to 0h Reset to 1 Reset to 0 Reset to 1 Reset to 0 Reset to 0
7.4.103 HEADER LOG REGISTER 1 - OFFSET 11Ch
BIT 7:0 15:8 23:16 31:24 FUNCTION Header Byte 3 Header Byte 2 Header Byte 1 Header Byte 0 TYPE ROS ROS ROS ROS DESCRIPTION Reset to 0 Reset to 0 Reset to 0 Reset to 0
7.4.104 HEADER LOG REGISTER 2 - OFFSET 120h
BIT 7:0 15:8 23:16 31:24 FUNCTION Header Byte 7 Header Byte 6 Header Byte 5 Header Byte 4 TYPE ROS ROS ROS ROS DESCRIPTION Reset to 0 Reset to 0 Reset to 0 Reset to 0
7.4.105 HEADER LOG REGISTER 3 - OFFSET 124h
BIT 7:0 15:8 23:16 31:24 FUNCTION Header Byte 11 Header Byte 10 Header Byte 9 Header Byte 8 TYPE ROS ROS ROS ROS DESCRIPTION Reset to 0 Reset to 0 Reset to 0 Reset to 0
7.4.106 HEADER LOG REGISTER 4 - OFFSET 128h
BIT 7:0 15:8 23:16 31:24 FUNCTION Header Byte 15 Header Byte 14 Header Byte 13 Header Byte 12 TYPE ROS ROS ROS ROS DESCRIPTION Reset to 0 Reset to 0 Reset to 0 Reset to 0
7.4.107 SECONDARY UNCORRECTABLE ERROR STATUS REGISTER - OFFSET 12Ch
BIT 0 1 2 3 4 5 FUNCTION Target Abort on Split Completion Status Master Abort on Split Completion Status Received Target Abort Status Received Master Abort Status Reserved Unexpected Split Completion Error Status TYPE RWCS RWCS RWCS RWCS RO RWCS DESCRIPTION Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0
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PI7C9X110
PCIe-to-PCI Reversible Bridge
BIT 6
7 8 9 10 11 12 13 31:14
FUNCTION Uncorrectable Split Completion Message Data Error Status Uncorrectable Data Error Status Uncorrectable Attribute Error Status Uncorrectable Address Error Status Delayed Transaction Discard Timer Expired Status PERR_L Assertion Detected Status SERR_L Assertion Detected Status Internal Bridge Error Status Reserved
TYPE RWCS
DESCRIPTION Reset to 0
RWCS RWCS RWCS RWCS RWCS RWCS RWCS RO
Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0
7.4.108 SECONDARY UNCORRECTABLE ERROR MASK REGISTER - OFFSET 130h
BIT 0 1 2 3 4 5 6 FUNCTION Target Abort on Split Completion Mask Master Abort on Split Completion Mask Received Target Abort Mask Received Master Abort Mask Reserved Unexpected Split Completion Error Mask Uncorrectable Split Completion Message Data Error Mask Uncorrectable Data Error Mask Uncorrectable Attribute Error Mask Uncorrectable Address Error Mask Delayed Transaction Discard Timer Expired Mask PERR_L Assertion Detected Mask SERR_L Assertion Detected Mask Internal Bridge Error Mask Reserved TYPE RWS RWS RWS RWS RO RWS RWS DESCRIPTION Reset to 0 Reset to 0 Reset to 0 Reset to 1 Reset to 0 Reset to 1 Reset to 0
7 8 9 10 11 12 13 31:14
RWS RWS RWS RWS RWS RWS RWS RO
Reset to 1 Reset to 1 Reset to 1 Reset to 1 Reset to 0 Reset to 1 Reset to 0 Reset to 0
7.4.109 SECONDARY UNCORRECTABLE ERROR SEVERITY REGISTER - OFFSET 134h
BIT 0 1 2 3 4 FUNCTION Target Abort on Split Completion Severity Master Abort on Split Completion Severity Received Target Abort Severity Received Master Abort Severity Reserved TYPE RWS RWS RWS RWS RO DESCRIPTION Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0
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PCIe-to-PCI Reversible Bridge
BIT 5 6
7 8 9 10 11 12 13 31:14
FUNCTION Unexpected Split Completion Error Severity Uncorrectable Split Completion Message Data Error Severity Uncorrectable Data Error Severity Uncorrectable Attribute Error Severity Uncorrectable Address Error Severity Delayed Transaction Discard Timer Expired Severity PERR_L Assertion Detected Severity SERR_L Assertion Detected Severity Internal Bridge Error Severity Reserved
TYPE RWS RWS
DESCRIPTION Reset to 0 Reset to 1
RWS RWS RWS RWS RWS RWS RWS RO
Reset to 0 Reset to 1 Reset to 1 Reset to 0 Reset to 0 Reset to 1 Reset to 0 Reset to 0
7.4.110 SECONDARY ERROR CAPABILITY AND CONTROL REGISTER - OFFSET 138h
BIT 4:0 31:5 FUNCTION Secondary First Error Pointer Reserved TYPE ROW RO DESCRIPTION Reset to 0 Reset to 0
7.4.111 SECONDARY HEADER LOG REGISTER - OFFSET 13Ch - 148h
BIT 35:0 FUNCTION Transaction Attribute TYPE ROS DESCRIPTION Transaction attribute, CBE [3:0] and AD [31:0] during attribute phase Reset to 0 Transaction command lower, CBE [3:0] during first address phase Reset to 0 Transaction command upper, CBE [3:0] during second address phase of DAC transaction Reset to 0 Reset to 0 Transaction address, AD [31:0] during first address phase Reset to 0 Transaction address, AD [31:0] during second address phase of DAC transaction Reset to 0
39:36
Transaction Command Lower Transaction Command Upper
ROS
43:40
ROS
63:44 95:64
Reserved Transaction Address
ROS ROS
127:96
Transaction Address
ROS
7.4.112 RESERVED REGISTER - OFFSET 14Ch 7.4.113 VC CAPABILITY ID REGISTER - OFFSET 150h
BIT 15:0 FUNCTION VC Capability ID TYPE RO DESCRIPTION Reset to 0002h
7.4.114 VC CAPABILITY VERSION REGISTER - OFFSET 150h
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PI7C9X110
PCIe-to-PCI Reversible Bridge
BIT 19:16
FUNCTION VC Capability Version
TYPE RO
DESCRIPTION Reset to 1h
7.4.115 NEXT CAPABILITY OFFSET REGISTER - OFFSET 150h
BIT 31:20 FUNCTION Next Capability Offset TYPE RO DESCRIPTION Next capability offset - the end of capabilities Reset to 0
7.4.116 PORT VC CAPABILITY REGISTER 1 - OFFSET 154h
BIT 2:0 3 6:4 7 9:8 11:10 31:12 FUNCTION Extended VC Count Reserved Low Priority Extended VC Count Reserved Reference Clock Port Arbitration Table Entry Size Reserved TYPE RO RO RO RO RO RO RO DESCRIPTION Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0
7.4.117 PORT VC CAPABILITY REGISTER 2 - OFFSET 158h
BIT 7:0 23:8 31:24 FUNCTION VC Arbitration Capability Reserved VC Arbitration Table Offset TYPE RO RO RO DESCRIPTION Reset to 0 Reset to 0 Reset to 0
7.4.118 PORT VC CONTROL REGISTER - OFFSET 15Ch
BIT 0 3:1 15:4 FUNCTION Load VC Arbitration Table VC Arbitration Select Reserved TYPE RO RO RO DESCRIPTION Reset to 0 Reset to 0 Reset to 0
7.4.119 PORT VC STATUS REGISTER - OFFSET 15Ch
BIT 16 31:17 FUNCTION VC Arbitration Table Status Reserved TYPE RO RO DESCRIPTION Reset to 0 Reset to 0
7.4.120 VC0 RESOURCE CAPABILITY REGISTER - OFFSET 160h
BIT 7:0 13:8 14 15 22:16 23 31:24 FUNCTION Port Arbitration Capability Reserved Advanced Packet Switching Reject Snoop Transactions Maximum Time Slots Reserved Port Arbitration Table Offset TYPE RO RO RO RO RO RO RO DESCRIPTION Reset to 0 Reset to 0 Reset to 0 Reset to0 Reset to 0 Reset to 0 Reset to 0
7.4.121 VC0 RESOURCE CONTROL REGISTER - OFFSET 164h
BIT FUNCTION TYPE DESCRIPTION
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PCIe-to-PCI Reversible Bridge
BIT 0 7:1 15:8 16 19:17 23:20 26:24 30:27 31
FUNCTION TC / VC Map TC / VC Map Reserved Load Port Arbitration Table Port Arbitration Select Reserved VC ID Reserved VC Enable
TYPE RO RW RO RO RO RO RO RO RO
DESCRIPTION For TC0 Reset to 1 For TC7 to TC1 Reset to 7Fh Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 1
7.4.122 VC0 RESOURCE STATUS REGISTER - OFFSET 168h
BIT 0 1 31:2 FUNCTION Port Arbitration Table 1 VC0 Negotiation Pending Reserved TYPE RO RO RO DESCRIPTION Reset to 0 Reset to 0 Reset to 0
7.4.123 RESERVED REGISTERS - OFFSET 16Ch - 300h 7.4.124 EXTRA GPI/GPO DATA AND CONTROL REGISTER - OFFSET 304h
BIT 3:0 7:4 11:8 15:12 19:16 31:20 FUNCTION Extra GPO Extra GPO Extra GPO enable Extra GPO enable Extra GPI Reserved TYPE RWC RWS RWC RWS RO RO DESCRIPTION GPO [3:0], write 1 to clear Reset to 0 GPO [3:0], write 1 to set Reset to 0 GPO [3:0] enable, write 1 to clear Reset to 0 GPO [3:0] enable, write 1 to set Reset to 0 Extra GPI [3:0] Data Register Reset to 0 Reset to 0
7.4.125 RESERVED REGISTERS - OFFSET 308h - 30Ch 7.4.126 REPLAY AND ACKNOWLEDGE LATENCY TIMERS - OFFSET 310h
BIT 11:0 12 15:13 29:16 30 31 FUNCTION Replay Timer Replay Timer Enable Reserved Acknowledge Latency Timer Acknowledge Latency Timer Enable Reserved TYPE RW RW RO RW RO RO DESCRIPTION Replay Timer Reset to 0 Replay Timer Enable Reset to 0 Reset to 0 Acknowledge Latency Timer Reset to 0 Acknowledge Latency Timer Enable Reset to 0 Reset to 0
7.4.127 RESERVED REGISTERS - OFFSET 314h - FFCh
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PCIe-to-PCI Reversible Bridge
7.5
PCI CONFIGURATION REGISTERS FOR NON-TRANSPARENT BRIDGE MODE
The following section describes the configuration space when the device is in non-transparent bridge mode. The descriptions for different register type are listed as follow:
Register Type RO ROS RW RWC RWS RWCS Descriptions Read Only Read Only and Sticky Read/Write Read/Write "1" to clear Read/Write and Sticky Read/Write "1" to clear and Sticky
7.5.1
VENDOR ID - OFFSET 00h
BIT 15:0 FUNCTION Vendor ID TYPE RO DESCRIPTION Identifies Pericom as the vendor of this device. Returns 12D8h when read.
7.5.2
DEVICE ID - OFFSET 00h
BIT 31:16 FUNCTION Device ID TYPE RO DESCRIPTION Identifies this device as the PI7C9X110. Returns E110 when read.
7.5.3
COMMAND REGISTER - OFFSET 04h
BIT 0 FUNCTION I/O Space Enable TYPE RW DESCRIPTION 0: Ignore I/O transactions on the primary interface 1: Enable response to memory transactions on the primary interface Reset to 0 0: Ignore memory read transactions on the primary interface 1: Enable memory read transactions on the primary interface Reset to 0 0: Do not initiate memory or I/O transactions on the primary interface and disable response to memory and I/O transactions on the secondary interface 1: Enable the bridge to operate as a master on the primary interfaces for memory and I/O transactions forwarded from the secondary interface. If the primary of the reverse bridge is PCI-X mode, the bridge is allowed to initiate a split completion transaction regardless of the status bit. Reset to 0 0: PI7C9X110 does not respond as a target to Special Cycle transactions, so this bit is defined as Read-Only and must return 0 when read Reset to 0 0: PI7C9X110 does not originate a Memory Write and Invalidate transaction. Implements this bit as Read-Only and returns 0 when read (unless forwarding a transaction for another master). This bit will be ignored in PCI-X mode. Reset to 0 This bit applies to reverse bridge only. 0: Ignore VGA palette access on the primary 1: Enable positive decoding response to VGA palette writes on the primary interface with I/O address bits AD [9:0] equal to 3C6h, 3C8h, and 3C9h (inclusive of ISA alias; AD [15:0] are not decoded and may be any value)
1
Memory Space Enable
RW
2
Bus Master Enable
RW
3
Special Cycle Enable
RO
4
Memory Write and Invalidate Enable
RO
5
VGA Palette Snoop Enable
RO / RW
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PI7C9X110
PCIe-to-PCI Reversible Bridge
BIT 6
FUNCTION Parity Error Response Enable
TYPE RW
DESCRIPTION Reset to 0 0: May ignore any parity error that is detected and take its normal action 1: This bit if set, enables the setting of Master Data Parity Error bit in the Status Register when poisoned TLP received or parity error is detected and takes its normal action Reset to 0 Wait cycle control not supported Reset to 0 0: Disable 1: Enable PI7C9X110 in forward bridge mode to report non-fatal or fatal error message to the Root Complex. Also, in reverse bridge mode to assert SERR_L on the primary interface Reset to 0 Fast back-to-back enable not supported Reset to 0 This bit applies to reverse bridge only. 0: INTA_L, INTB_L, INTC_L, and INTD_L can be asserted on PCI interface 1: Prevent INTA_L, INTB_L, INTC_L, and INTD_L from being asserted on PCI interface Reset to 0 Reset to 00000
7
Wait Cycle Control
RO
8
SERR_L Enable Bit
RW
9
Fast Back-to-Back Enable
RO
10
Interrupt Disable
RO / RW
15:11
Reserved
RO
7.5.4
PRIMARY STATUS REGISTER - OFFSET 04h
BIT 18:16 19 FUNCTION Reserved Primary Interrupt Status TYPE RO RO DESCRIPTION Reset to 000 0: No INTx interrupt message request pending in PI7C9X110 primary 1: INTx interrupt message request pending in PI7C9X110 primary Reset to 0 1: PI7C9X110 supports the capability list (offset 34h in the pointer to the data structure) Reset to 1 This bit applies to reverse bridge only. 1: 66MHz capable Reset to 0 when forward bridge or 1 when reverse bridge. Reset to 0 This bit applies to reverse bridge only. 1: Enable fast back-to-back transactions Reset to 0 when forward bridge or 1 when reverse bridge with primary bus in PCI mode
20
Capability List Capable
RO
21
66MHz Capable
RO
22 23
Reserved Fast Back-to-Back Capable
RO RO
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PI7C9X110
PCIe-to-PCI Reversible Bridge
BIT 24
FUNCTION Master Data Parity Error Detected
TYPE RWC
DESCRIPTION Bit set if its Parity Error Enable bit is set and either of the conditions occurs on the primary: FORWARD BRIDGE - * Receives a completion marked poisoned * Poisons a write request REVERSE BRIDGE - * Detected parity error when receiving data or Split Response for read * Observes P_PERR_L asserted when sending data or receiving Split Response for write * Receives a Split Completion Message indicating data parity error occurred for non-posted write Reset to 0 These bits apply to reverse bridge only. 00: 01: 10: 11: fast DEVSEL_L decoding medium DEVSEL_L decoding slow DEVSEL_L decoding reserved
26:25
DEVSEL_L Timing (medium decode)
RO
27
Signaled Target Abort
RWC
Reset to 00 when forward bridge or 01 when reverse bridge. FORWARD BRIDGE - This bit is set when PI7C9X110 completes a request using completer abort status on the primary REVERSE BRIDGE - This bit is set to indicate a target abort on the primary Reset to 0 FORWARD BRIDGE - This bit is set when bridge receives a completion with completer abort completion status on the primary REVERSE BRIDGE - This bit is set when PI7C9X110 detects a target abort on the primary Reset to 0 FORWARD BRIDGE - This bit is set when PI7C9X110 receives a completion with unsupported request completion status on the primary REVERSE BRIDGE - This bit is set when PI7C9X110 detects a master abort on the primary FORWARD BRIDGE - This bit is set when PI7C9X110 sends an ERR_FATAL or ERR_NON_FATAL message on the primary REVERSE BRIDGE - This bit is set when PI7C9X110 asserts SERR_L on the primary Reset to 0 FORWARD BRIDGE - This bit is set when poisoned TLP is detected on the primary REVERSE BRIDGE - This bit is set when address or data parity error is detected on the primary Reset to 0
28
Received Target Abort
RWC
29
Received Master Abort
RWC
30
Signaled System Error
RWC
31
Detected Parity Error
RWC
7.5.5
REVISION ID REGISTER - OFFSET 08h
BIT 7:0 FUNCTION Revision TYPE RO DESCRIPTION Reset to 00000002h
7.5.6
CLASS CODE REGISTER - OFFSET 08h
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PI7C9X110
PCIe-to-PCI Reversible Bridge
BIT 15:8
FUNCTION Programming Interface
TYPE RO
DESCRIPTION Subtractive decoding of PCI-PCI bridge not supported Reset to 00000000 Sub-Class Code 10000000: Other bridge Reset to 10000000 Base class code 00000110: Bridge Device (transparent mode) Reset to 00000110 (transparent mode)
23:16
Sub-Class Code
RO
31:24
Base Class Code
RO
7.5.7
CACHE LINE SIZE REGISTER - OFFSET 0Ch
BIT 1:0 FUNCTION Reserved TYPE RO DESCRIPTION Bit [1:0] not supported Reset to 00 1: Cache line size = 4 double words Reset to 0 1: Cache line size = 8 double words Reset to 0 1: Cache line size = 16 double words Reset to 0 1: Cache line size = 32 double words Reset to 0 Bit [7:6] not supported Reset to 00
2
Cache Line Size
RW
3
Cache Line Size
RW
4
Cache Line Size
RW
5
Cache Line Size
RW
7:6
Reserved
RO
7.5.8
PRIMARY LATENCY TIMER REGISTER - OFFSET 0Ch
BIT 15:8 FUNCTION Primary Latency Timer TYPE RO / RW DESCRIPTION 8 bits of primary latency timer in PCI/PCI-X FORWARD BRIDGE - RO with reset to 00h REVERSE BRIDGE - RW with reset to 00h in PCI mode or 40h in PCI-X mode
7.5.9
PRIMARY HEADER TYPE REGISTER - OFFSET 0Ch
BIT 22:16 23 FUNCTION Other bridge configuration (non-transparent mode) Single Function Device TYPE RO RO DESCRIPTION Type-0 header format configuration (10-3Fh) Reset to 0000000 (non-transparent mode) 0: Indicates single function device Reset to 0 Reset to 00h
31:24
Reserved
RO
7.5.10 PRIMARY CSR AND MEMORY 0 BASE ADDRESS REGISTER - OFFSET 10h
BIT 0 FUNCTION Space Indicator TYPE RO DESCRIPTION 0: Memory space 1: IO space
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PCIe-to-PCI Reversible Bridge
BIT
FUNCTION
TYPE
DESCRIPTION Reset to 0 00: 32-bit address decode range 01: 64-bit address decode range 10 and 11: reserved Reset to 00 0: Memory space is non-prefetchable 1: Memory space is prefetchable Reset to 0 Reset to 0 The size and type of this Base Address Register are defined from Downstream Memory 0 Setup Register (Offset 9Ch), which can be initialized by EEPROM (I2C) or SM Bus or Local Processor. The range of this register is from 4KB to 2GB. The lower 4KB if this address reange map to the PI7C9X110 CSRs into memory space. The remaining space is this range above 4KB, if any, specifies a range for forwarding downstream memory transactions. PI7X9X110 uses downstream Memory 0 Translated Base Register (Offset 98h) to formulate direct address translation. If a bit in the setup register is set to one, then the correspondent bit of this register will be changed to RW. Reset to 00000h
2:1
Address Type
RO
3
Prefetchable control
RO
11:4 31:12
Reserved Base Address
RO RW/RO
7.5.11 PRIMARY CSR I/O BASE ADDRESS REGISTER - OFFSET 14h
BIT 0 FUNCTION Space Indicator TYPE RO DESCRIPTION 0: Memory space 1: IO space Reset to 1 Reset to 0 This Base Address Register maps to PI7C9X110 primary IO space. The maximum size is 256 bytes. Reset to 00000000h
7:1 31:8
Reserved Base Address
RO RO/RW
7.5.12 DOWNSTREAM I/O OR MEMORY 1 BASE ADDRESS REGISTER - OFFSET 18h
BIT 0 FUNCTION Space Indicator TYPE RO DESCRIPTION 0: Memory space 1: IO space Reset to 0 00: 32-bit address decode range 01: 64-bit address decode range 10 and 11: reserved Reset to 00 0: Memory space is non-prefetchable 1: Memory space is prefetchable Reset to 0 Reset to 0 The size and type of this Base Address Register are defined from Downstream IO or Memory 1 Setup Register (Offset ACh), which can be initialized by EEPROM (I2C) or SM Bus or Local Processor. Writing a zero to bit [31] of the setup register to disable this register. The range of this register is from 4KB to 2GB for memory space or from 64B to 256B for IO space. PI7X9X110 uses downstream IO or Memory 1 Translated Base Register (Offset A8h) to formulate direct address translation. If a bit in the
2:1
Address Type
RO
3
Prefetchable control
RO
11:4 31:12
Reserved Base Address
RO RW/RO
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PI7C9X110
PCIe-to-PCI Reversible Bridge
BIT
FUNCTION
TYPE
DESCRIPTION setup register is set to one, then the correspondent bit of this register will be changed to RW. Reset to 00000h
7.5.13 DONWSTREAM MEMORY 2 BASE ADDRESS REGISTER - OFFSET 1Ch
BIT 0 FUNCTION Space Indicator TYPE RO DESCRIPTION 0: Memory space 1: IO space Reset to 0 00: 32-bit address decode range 01, 10 and 11: reserved Reset to 00 0: Memory space is non-prefetchable 1: Memory space is prefetchable Reset to 0 Reset to 0 The size and type of this Base Address Register are defined from Downstream Memory 2 Setup Register (CSR Offset 00Ch), which can be initialized by EEPROM (I2C) or SM Bus or Local Processor. Writing a zero to bit [31] of the setup register to disable this register. The range of this register is from 4KB to 2GB for memory space. PI7X9X110 uses downstream Memory 2 Translated Base Register (CSR Offset 008h) to formulate direct address translation. If a bit in the setup register is set to one, then the correspondent bit of this register will be changed to RW. Reset to 00000h
2:1
Address Type
RO
3
Prefetchable control
RO
11:4 31:12
Reserved Base Address
RO RW/RO
7.5.14 DOWNSTREAM MEMORY 3 BASE ADDRESS REGISTER - OFFSET 20h
BIT 0 FUNCTION Space Indicator TYPE RO DESCRIPTION 0: Memory space 1: IO space Reset to 0 00: 32-bit address decode range 01: 64-bit address decode range 10 and 11: reserved Reset to 00 0: Memory space is non-prefetchable 1: Memory space is prefetchable Reset to 0 Reset to 0 The size and type of this Base Address Register are defined from Downstream Memory 3 Setup Register (CSR Offset 014h), which can be initialized by EEPROM (I2C) or SM Bus or Local Processor. Writing a zero to bit [31] of the setup registers (CSR Offset 014h and 018h) to disable this register. The range of this register is from 4KB to 9EB for memory space. PI7C9X110 uses Memory 3 Translated Base Register (CSR Offset 010h) to formulate direct address translation when 32-bit addressing programmed. When 64-bit addressing programmed, no address translation is performed. If a bit in the setup register is set to one, then the correspondent bit of this register will be changed to RW. Reset to 00000h
2:1
Address Type
RO
3
Prefetchable control
RO
11:4 31:12
Reserved Base Address
RO RW/RO
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PI7C9X110
PCIe-to-PCI Reversible Bridge
7.5.15 DOWNSTREAM MEMORY 3 UPPER BASE ADDRESS REGISTER - OFFSET 24h
BIT 31:0 FUNCTION Base address TYPE RO/RW DESCRIPTION The size of this Base Address Register is defined from Downstream Memory 3 Upper 32-bit Setup Register (CSR Offset 018h), which can be initialized by EEPROM (I2C) or SM Bus or Local Processor. Writing a zero to bit [31] of the setup registers (CSR Offset 018h) to disable this register. This register defines the upper 32 bits of a memory range for downstream forwarding memory. If a bit in the setup register is set to one, then the correspondent bit of this register will be changed to RW. Reset to 00000000h
7.5.16 RESERVED REGISTER - OFFSET 28h 7.5.17 SUBSYTEM ID AND SUBSYSTEM VENDOR ID REGISTER - OFFSET 2Ch
BIT 15:0 FUNCTION Subsystem Vendor ID TYPE RO DESCRIPTION Identify the vendor ID for add-in card or subsystem Reset to 0000h Identify the vendor specific device ID for add-in card or subsystem Reset to 0000h
31:16
Subsystem ID
RO
7.5.18 RESERVED REGISTER - OFFSET 30h 7.5.19 CAPABILITY POINTER - OFFSET 34h
BIT 31:8 7:0 FUNCTION Reserved Capability Pointer TYPE RO RO DESCRIPTION Reset to 0 Capability pointer to 80h Reset to 80h
7.5.20 EXPANSION ROM BASE ADDRESS REGISTER - OFFSET 38h
BIT 31:0 FUNCTION Expansion ROM Base Address TYPE RO DESCRIPTION Expansion ROM not supported. Reset to 00000000h
7.5.21 PRIMARY INTERRUPT LINE REGISTER - OFFSET 3Ch
BIT 7:0 FUNCTION Primary Interrupt Line TYPE RW DESCRIPTION These bits apply to reverse bridge only. For initialization code to program to tell which input of the interrupt controller the PI7C9X110's INTA_L in connected to. Reset to 00000000
7.5.22 PRIMARY INTERRUPT PIN REGISTER - OFFSET 3Ch
BIT FUNCTION TYPE DESCRIPTION
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PI7C9X110
PCIe-to-PCI Reversible Bridge
BIT 15:8
FUNCTION Primary Interrupt Pin
TYPE RO
DESCRIPTION These bits apply to reverse bridge only. Designates interrupt pin INTA_L, is used Reset to 00h when forward mode or 01h when reverse mode.
7.5.23 PRIMARY MINIMUM GRANT REGISTER - OFFSET 3Ch
BIT 23:16 FUNCTION Primary Minimum Grant TYPE RO DESCRIPTION This register is valid only in reverse bridge mode. It specifies how long of a burst period that PI7C9X110 needs on the primary bus in the units of 1/4 microseconds. Reset to 0
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PI7C9X110
PCIe-to-PCI Reversible Bridge
7.5.24 PRIMARY MAXIMUM LATENCY TIME REGISTER - OFFSET 3Ch
BIT 31:24 FUNCTION Primary Maximum Latency Timer TYPE RO DESCRIPTION This register is valid only in reverse bridge mode. It specifies how often that PI7C9X110 needs to gain access to the primary bus in units of 1/4 microseconds. Reset to 0
7.5.25 PCI DATA BUFFERING CONTROL REGISTER - OFFSET 40h
BIT 0 FUNCTION Secondary Internal Arbiter's PARK Function TYPE RW DESCRIPTION 0: Park to the last master 1: Park to PI7C9X110 secondary port Reset to 0 0: Enable memory read prefetching dynamic control for PCI to PCIe read 1: Disable memory read prefetching dynamic control for PCI to PCIe read Reset to 0 0: Enable completion data prediction for PCI to PCIe read. 1: Disable completion data prediction Reset to 0 Reset to 0 These two bits are ignored in PCI-X mode. 00: One cache line prefetch if memory read multiple address is in prefetchable range at the PCI interface 01: Full prefetch if address is in prefetchable range at PCI interface, and the PI7C9X110 will keep remaining data after it disconnects the external master during burst read with read multiple command until the discard timer expires 10: Full prefetch if address is in prefetchable range at PCI interface 11: Full prefetch if address is in prefetchable range at PCI interface and the PI7C9X110 will keep remaining data after the read multiple is terminated either by an external master or by the PI7C9X110, until the discard time expires Reset to 10 These two bits are ignored in PCI-X mode. 00: Once cache line prefetch if memory read address is in prefetchable range at PCI interface 01: Full prefetch if address is in prefetchable range at PCI interface and the PI7C9X110 will keep remaining data after it is disconnected by an external master during burst read with read line command, until discard timer expires 10: Full prefetch if memory read line address is in prefetchable range at PCI interface 11: Full prefetch if address is in prefetchable range at PCI interface and the PI7C9X110 will keep remaining data after the read line is terminated either by an external master or by the PI7C9X110, until the discard timer expires Reset to 00
1
Memory Read Prefetching Dynamic Control Disable
RW
2
Completion Data Prediction Control
RW
3 5:4
Reserved PCI Read Multiple Prefetch Mode
RO RW
7:6
PCI Read Line Prefetch Mode
RW
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PI7C9X110
PCIe-to-PCI Reversible Bridge
BIT 9:8
FUNCTION PCI Read Prefetch Mode
TYPE RW
DESCRIPTION 00: One cache line prefetch if memory read address is in prefetchable range at PCI interface 01: Reserved 10: Full prefetch if memory read address is in prefetchable range at PCI interface 11: Disconnect on the first DWORD Reset to 00 0: Retry any master at PCI bus that repeats its transaction with command code changes. 1: Allows any master at PCI bus to change memory command code (MR, MRL, MRM) after it has received a retry. The PI7C9X110 will complete the memory read transaction and return data back to the master if the address and byte enables are the same. Reset to 0 Reset to 0 Maximum byte count is used by the PI7C9X110 when generating memory read requests on the PCIe link in response to a memory read initiated on the PCI bus and bit [9:8], bit [7:6], and bit [5:4] are set to "full prefetch". 000: 001: 010: 011: 100: 101: 110: 111: 512 bytes (default) 128 bytes 256 bytes 512 bytes 1024 bytes 2048 bytes 4096 bytes 512 bytes
10
PCI Special Delayed Read Mode Enable
RW
11 14:12
Reserved Maximum Memory Read Byte Count
RO RW
Reset to 000
7.5.26 CHIP CONTROL 0 REGISTER - OFFSET 40h
BIT 15 FUNCTION Flow Control Update Control TYPE RW DESCRIPTION 0: Flow control is updated for every two credits available 1: Flow control is updated for every on credit available Reset to 0 0: The PCI retry counter has not expired since the last reset 1: The PCI retry counter has expired since the last reset Reset to 0 00: No expiration limit 01: Allow 256 retries before expiration 10: Allow 64K retries before expiration 11: Allow 2G retries before expiration Reset to 00 0: Enable the PCI discard timer in conjunction with bit [27] offset 3Ch (bridge control register) 1: Disable the PCI discard timer in conjunction with bit [27] offset 3Ch (bridge control register) Reset to 0
16
PCI Retry Counter Status
RWC
18:17
PCI Retry Counter Control
RW
19
PCI Discard Timer Disable
RW
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PI7C9X110
PCIe-to-PCI Reversible Bridge
BIT 20
FUNCTION PCI Discard Timer Short Duration
TYPE RW
DESCRIPTION 0: Use bit [24] offset 3Ch for forward bridge or bit [25] offset 3Ch for reverse bridge to indicate how many PCI clocks should be allowed before the PCI discard timer expires 1: 64 PCI clocks allowed before the PCI discard timer expires Reset to 0 00: Timer expires at 25us 01: Timer expires at 0.5ms 10: Timer expires at 5ms 11: Timer expires at 25ms Reset to 01 0: Enable out-of-order capability between delayed transactions 1: Disable out-of-order capability between delayed transactions Reset to 0 00: Timer expires at 50us 01: Timer expires at 10ms 10: Timer expires at 50ms 11: Timer disabled Reset to 01 0: All memory transactions from PCI-X to PCIe will be mapped to TC0 1: All memory transactions from PCI-X to PCIe will be mapped to Traffic Class defined in bit [29:27] of offset 40h. Reset to 0 Reset to 001 0: Normal mode 1: Enable serial link interface loopback mode (TX to RX) if TM0=LOW, TM1=HIGH, TM2=HIGH, MSK_IN=HIGH, REVRSB=HIGH. PCI transaction from PCI bus will loop back to PCI bus RO for forward bridge Reset to 0 0: PI7C9X110 configuration space can be accessed from both interfaces 1: PI7C9X110 configuration space can only be accessed from the secondary interface. Primary bus accessed receives completion with CRS status for forward bridge, or target retry for reverse bridge Reset to 0 if TM0 is LOW
22:21
Configuration Request Retry Timer Counter Value Control
RW
23
Delayed Transaction Order Control
RW
25:24
Completion Timer Counter Value Control
RW
26
Isochronous Traffic Support Enable
RW
29:27 30
Traffic Class Used For Isochronous Traffic Serial Link Interface Loopback Enable
RW RW / RO
31
Primary Configuration Access Lockout
RO / RW
7.5.27 SECONDARY COMMAND REGISTER - OFFSET 44h
BIT 0 FUNCTION I/O Space Enable TYPE RW DESCRIPTION 0: Ignore I/O transactions on the secondary interface 1: Enable response to memory transactions on the secondary interface Reset to 0 0: Ignore memory read transactions on the secondary interface 1: Enable memory read transactions on the secondary interface Reset to 0
1
Memory Space Enable
RW
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PI7C9X110
PCIe-to-PCI Reversible Bridge
BIT 2
FUNCTION Bus Master Enable
TYPE RW
DESCRIPTION 0: Do not initiate memory or I/O transactions on the secondary interface and disable response to memory and I/O transactions on the secondary interface 1: Enable the PI7C9X110 to operate as a master on the secondary interfaces for memory and I/O transactions forwarded from the secondary interface. If the secondary of the reverse bridge is PCI-X mode, the PI7C9X110 is allowed to initiate a split completion transaction regardless of the status bit. Reset to 0 0: Bridge does not respond as a target to Special Cycle transactions, so this bit is defined as Read-Only and must return 0 when read Reset to 0 0: PI7C9X110 does not originate a Memory Write and Invalidate transaction. Implements this bit as Read-Only and returns 0 when read (unless forwarding a transaction for another master). This bit will be ignored in PCI-X mode. Reset to 0 0: Ignore VGA palette snoop access on the secondary Reset to 0 0: May ignore any parity error that is detected and take its normal action 1: This bit if set, enables the setting of Master Data Parity Error bit in the Status Register when poisoned TLP received or parity error is detected and takes its normal action Reset to 0 Wait cycle control not supported Reset to 0 0: Disable 1: Enable PI7C9X110 in forward bridge mode to report non-fatal or fatal error message to the Root Complex. Also, in reverse bridge mode to assert SERR_L on the secondary interface Reset to 0 Fast back-to-back enable not supported Reset to 0 0: INTx interrupt messages can be generated 1: Prevent INTx messages to be generated and any asserted INTx interrupts will be released. Reset to 0 Reset to 00000
3
Special Cycle Enable
RO
4
Memory Write and Invalidate Enable
RO
5
VGA Palette Snoop Enable
RO
6
Parity Error Response Enable
RW
7
Wait Cycle Control
RO
8
Secondary SERR_L Enable Bit
RW
9
Fast Back-to-Back Enable
RO
10
Secondary Interrupt Disable
RO / RW
15:11
Reserved
RO
7.5.28 SECONDARY STATUS REGISTER - OFFSET 44h
BIT 18:16 19 FUNCTION Reserved Secondary Interrupt Status TYPE RO RO DESCRIPTION Reset to 000 0: No INTx interrupt message request pending in PI7C9X110 secondary 1: INTx interrupt message request pending in PI7C9X110 secondary Reset to 0 1: PI7C9X110 supports the capability list (offset 34h in the pointer to the data structure) Reset to 1
20
Capability List Capable
RO
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PI7C9X110
PCIe-to-PCI Reversible Bridge
BIT 21
FUNCTION 66MHz Capable
TYPE RO
DESCRIPTION This bit applies to forward bridge only. 1: 66MHz capable Reset to 0 when reverse bridge or 1 when forward bridge. Reset to 0 This bit applies to forward bridge only. 1: Enable fast back-to-back transactions Reset to 0 when reverse bridge or 1 when forward bridge with secondary bus in PCI mode Bit set if its Parity Error Enable bit is set and either of the conditions occurs on the secondary: REVERSE BRIDGE - * Receives a completion marked poisoned * Poisons a write request FORWARD BRIDGE - * Detected parity error when receiving data or Split Response for read * Observes P_PERR_L asserted when sending data or receiving Split Response for write * Receives a Split Completion Message indicating data parity error occurred for non-posted write Reset to 0 These bits apply to forward bridge only. 00: 01: 10: 11: fast DEVSEL_L decoding medium DEVSEL_L decoding slow DEVSEL_L decoding reserved
22 23
Reserved Fast Back-to-Back Capable
RO RO
24
Master Data Parity Error Detected
RWC
26:25
DEVSEL_L Timing (medium decode)
RO
27
Signaled Target Abort
RWC
Reset to 00 when reverse bridge or 01 when forward bridge. REVERSE BRIDGE - This bit is set when PI7C9X110 completes a request using completer abort status on the secondary FORWARD BRIDGE - This bit is set to indicate a target abort on the secondary Reset to 0 REVERSE BRIDGE - This bit is set when bridge receives a completion with completer abort completion status on the secondary FORWARD BRIDGE - This bit is set when PI7C9X110 detects a target abort on the secondary Reset to 0 REVERSE BRIDGE - This bit is set when PI7C9X110 receives a completion with unsupported request completion status on the secondary FORWARD BRIDGE - This bit is set when PI7C9X110 detects a master abort on the secondary REVERSE BRIDGE - This bit is set when PI7C9X110 sends an ERR_FATAL or ERR_NON_FATAL message on the secondary FORWARD BRIDGE - This bit is set when PI7C9X110 asserts SERR_L on the secondary Reset to 0
28
Received Target Abort
RWC
29
Received Master Abort
RWC
30
Signaled System Error
RWC
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PI7C9X110
PCIe-to-PCI Reversible Bridge
BIT 31
FUNCTION Detected Parity Error
TYPE RWC
DESCRIPTION REVERSE BRIDGE - This bit is set when poisoned TLP is detected on the secondary FORWARD BRIDGE - This bit is set when address or data parity error is detected on the secondary Reset to 0
7.5.29 ARBITER ENABLE REGISTER - OFFSET 48h
BIT 0 FUNCTION Enable Arbiter 0 TYPE RW DESCRIPTION 0: Disable arbitration for internal PI7C9X110request 1: Enable arbitration for internal PI7C9X110 request Reset to 1 0: Disable arbitration for master 1 1: Enable arbitration for master 1 Reset to 1 0: Disable arbitration for master 2 1: Enable arbitration for master 2 Reset to 1 0: Disable arbitration for master 3 1: Enable arbitration for master 3 Reset to 1 0: Disable arbitration for master 4 1: Enable arbitration for master 4 Reset to 1 0: Disable arbitration for master 5 1: Enable arbitration for master 5 Reset to 1 0: Disable arbitration for master 6 1: Enable arbitration for master 6 Reset to 1 0: Disable arbitration for master 7 1: Enable arbitration for master 7 Reset to 1 0: Disable arbitration for master 8 1: Enable arbitration for master 8 Reset to 1
1
Enable Arbiter 1
RW
2
Enable Arbiter 2
RW
3
Enable Arbiter 3
RW
4
Enable Arbiter 4
RW
5
Enable Arbiter 5
RW
6
Enable Arbiter 6
RW
7
Enable Arbiter 7
RW
8
Enable Arbiter 8
RW
7.5.30 ARBITER MODE REGISTER - OFFSET 48h
BIT 9 FUNCTION External Arbiter Bit TYPE RO DESCRIPTION 0: Enable internal arbiter (if CFN_L is tied LOW) 1: Use external arbiter (if CFN_L is tied HIGH) Reset to 0/1 according to what CFN_L is tied to 0: Broken master timeout disable 1: This bit enables the internal arbiter to count 16 PCI bus cycles while waiting for FRAME_L to become active when a device's PCI bus GNT is active and the PCI bus is idle. If the broken master timeout expires, the PCI bus GNT for the device is de-asserted. Reset to 0
10
Broken Master Timeout Enable
RW
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PI7C9X110
PCIe-to-PCI Reversible Bridge
BIT 11
FUNCTION Broken Master Refresh Enable
TYPE RW
DESCRIPTION 0: A broken master will be ignored forever after de-asserting its REQ_L for at least 1 clock 1: Refresh broken master state after all the other masters have been served once Reset to 0 08h: These bits are the initialization value of a counter used by the internal arbiter. It controls the number of PCI bus cycles that the arbiter holds a device's PCI bus GNT active after detecting a PCI bus REQ_L from another device. The counter is reloaded whenever a new PCI bus GNT is asserted. For every new PCI bus GNT, the counter is armed to decrement when it detects the new fall of FRAME_L. If the arbiter fairness counter is set to 00h, the arbiter will not remove a device's PCI bus GNT until the device has deasserted its PCI bus REQ. Reset to 08h 0: GNT_L not de-asserted after granted master assert FRAME_L 1: GNT_L de-asserts for 1 clock after 2 clocks of the granted master asserting FRAME_L Reset to 0 Reset to 0
19:12
Arbiter Fairness Counter
RW
20
GNT_L Output Toggling Enable
RW
21
Reserved
RO
7.5.31 ARBITER PRIORITY REGISTER - OFFSET 48h
BIT 22 FUNCTION Arbiter Priority 0 TYPE RW DESCRIPTION 0: Low priority request to internal PI7C9X110 1: High priority request to internal PI7C9X110 Reset to 1 0: Low priority request to master 1 1: High priority request to master 1 Reset to 0 0: Low priority request to master 2 1: High priority request to master 2 Reset to 0 0: Low priority request to master 3 1: High priority request to master 3 Reset to 0 0: Low priority request to master 4 1: High priority request to master 4 Reset to 0 0: Low priority request to master 5 1: High priority request to master 5 Reset to 0 0: Low priority request to master 6 1: High priority request to master 6 Reset to 0 0: Low priority request to master 7 1: High priority request to master 7 Reset to 0
23
Arbiter Priority 1
RW
24
Arbiter Priority 2
RW
25
Arbiter Priority 3
RW
26
Arbiter Priority 4
RW
27
Arbiter Priority 5
RW
28
Arbiter Priority 6
RW
29
Arbiter Priority 7
RW
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PI7C9X110
PCIe-to-PCI Reversible Bridge
BIT 30
FUNCTION Arbiter Priority 8
TYPE RW
DESCRIPTION 0: Low priority request to master 8 1: High priority request to master 8 Reset to 0 Reset to 0
31
Reserved
RO
7.5.32 SECONDARY CACHE LINE SIZE REGISTER - OFFSET 4Ch
BIT 1:0 FUNCTION Reserved TYPE RO DESCRIPTION 00: Cache line size of 1 DW and 2 DW are not supported Reset to 00 1: Cache line size = 4 double words Reset to 0 1: Cache line size = 8 double words Reset to 0 1: Cache line size = 16 double words Reset to 0 1: Cache line size = 32 double words Reset to 0 Bit [7:6] not supported Reset to 00
2
Cache Line Size
RW
3
Cache Line Size
RW
4
Cache Line Size
RW
5
Cache Line Size
RW
7:6
Reserved
RO
7.5.33 SECONDARY LATENCY TIME REGISTER - OFFSET 4Ch
BIT 15:8 FUNCTION Secondary Latency Timer TYPE RO / RW DESCRIPTION 8 bits of secondary latency timer in PCI/PCI-X REVERSE BRIDGE - RO with reset to 00h FORWARD BRIDGE - RW with reset to 00h in PCI mode or 40h in PCI-X mode
7.5.34 SECONDARY HEADER TYPE REGISTER - OFFSET 4Ch
BIT 22:16 FUNCTION Other Bridge Configuration TYPE RO DESCRIPTION Type-0 header format configuration (10 - 3Fh) Reset to 0000000 0: Indicates single function device Reset to 0 Reset to 00h
23
Single Function Device
RO
31:24
Reserved
RO
7.5.35 SECONDARY CSR AND MEMORY 0 BASE ADDRESS REGISTER - OFFSET 50h
BIT 0 FUNCTION Space Indicator TYPE RO DESCRIPTION 0: Memory space 1: IO space Reset to 0
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PI7C9X110
PCIe-to-PCI Reversible Bridge
BIT 2:1
FUNCTION Address Type
TYPE RO
DESCRIPTION 00: 32-bit address decode range 01: 64-bit address decode range 10 and 11: reserved Reset to 00 0: Memory space is non-prefetchable 1: Memory space is prefetchable Reset to 0 Reset to 0 The size and type of this Base Address Register are defined from Upstream Memory 0 Setup Register (Offset E4h), which can be initialized by EEPROM (I2C) or SM Bus or Local Processor. The range of this register is from 4KB to 2GB. The lower 4KB if this address reange map to the PI7C9X110 CSRs into memory space. The remaining space is this range above 4KB, if any, specifies a range for forwarding upstream memory transactions. PI7X9X110 uses upstream Memory 0 Translated Base Register (Offset E0h) to formulate direct address translation. If a bit in the setup register is set to one, then the correspondent bit of this register will be changed to RW. Reset to 00000h
3
Prefetchable control
RO
11:4 31:12
Reserved Base Address
RO RW/RO
7.5.36 SECONDARY CSR I/O BASE ADDRESS REGISTER - OFFSET 54h
BIT 0 FUNCTION Space Indicator TYPE RO DESCRIPTION 0: Memory space 1: IO space Reset to 1 Reset to 0 This Base Address Register maps to PI7C9X110 secondary IO space. The maximum size is 256 bytes. Reset to 00000000h
7:1 31:8
Reserved Base Address
RO RO/RW
7.5.37 UPSTREAM I/O OR MEMORY 1 BASE ADDRESS REGISTER - OFFSET 58h
BIT 0 FUNCTION Space Indicator TYPE RO DESCRIPTION 0: Memory space 1: IO space Reset to 0 00: 32-bit address decode range 01: 64-bit address decode range 10 and 11: reserved Reset to 00 0: Memory space is non-prefetchable 1: Memory space is prefetchable Reset to 0 Reset to 0
2:1
Address Type
RO
3
Prefetchable control
RO
5:4
Reserved
RO
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PI7C9X110
PCIe-to-PCI Reversible Bridge
BIT 31:6
FUNCTION Base Address
TYPE RW/RO
DESCRIPTION The size and type of this Base Address Register are defined from Upstream IO or Memory 1 Setup Register (Offset ECh), which can be initialized by EEPROM (I2C) or SM Bus or Local Processor. Writing a zero to bit [31] of the setup register to disable this register. The range of this register is from 4KB to 2GB for memory space or from 64B to 256B for IO space. PI7X9X110 uses upstream IO or Memory 1 Translated Base Register (Offset E8h) to formulate direct address translation. If a bit in the setup register is set to one, then the correspondent bit of this register will be changed to RW. Reset to 00000h
7.5.38 UPSTREAM MEMORY 2 BASE ADDRESS REGISTER - OFFSET 5Ch
BIT 0 FUNCTION Space Indicator TYPE RO DESCRIPTION 0: Memory space 1: IO space Reset to 0 00: 32-bit address decode range 01, 10 and 11: reserved Reset to 00 0: Memory space is non-prefetchable 1: Memory space is prefetchable Reset to 0 Reset to 0 This Base Address register defines the address range for upstream memory transactions. PI7C9X110 uses a lookup table to do the address translation. The address range of this register is from 16KB to 2GB in memory space. The address range is divided into 64 pages. The size of each page is defined by Memory Address Forwarding Control register (Offset 6Ah), which is initialized by EEPROM (I2C) or SM Bus or local processor. Writing a zero to the bit [0] of the look up table entry can disable the corresponding page of this register (CSR Offset 1FFh: 100h). The number of writeable bit may change depending on the page size setup. Reset to 00000h
2:1
Address Type
RO
3
Prefetchable control
RO
13:4 31:14
Reserved Base Address
RO RW/RO
7.5.39 UPSTREAM MEMORY 3 BASE ADDRESS REGISTER - OFFSET 60h
BIT 0 FUNCTION Space Indicator TYPE RO DESCRIPTION 0: Memory space 1: IO space Reset to 0 00: 32-bit address decode range 01: 64-bit address decode range 10 and 11: reserved Reset to 00 0: Memory space is non-prefetchable 1: Memory space is prefetchable Reset to 0 Reset to 0
2:1
Address Type
RO
3
Prefetchable control
RO
11:4
Reserved
RO
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PI7C9X110
PCIe-to-PCI Reversible Bridge
BIT 31:12
FUNCTION Base Address
TYPE RW/RO
DESCRIPTION The size and type of this Base Address Register are defined from Upstream Memory 3 Setup Register (CSR Offset 034h), which can be initialized by EEPROM (I2C) or SM Bus or Local Processor. Writing a zero to bit [31] of the setup registers (CSR Offset 034h and 038h) to disable this register. The range of this register is from 4KB to 9EB for memory space. PI7C9X110 uses this register and the Upstream Memory 3 Upper Base Address Register when 64-bit addressing programmed (bit [21] of Offset 68h). When 64-bit addressing is disabled, no address translation is performed. All 64-bit address transactions on the secondary interface falling outside of the Downstream Memory 3 address range are forwarded upstream. Reset to 00000h
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PI7C9X110
PCIe-to-PCI Reversible Bridge
7.5.40 UPSTREAM MEMORY 3 UPPER BASE ADDRESS REGISTER - OFFSET 64h
BIT 31:0 FUNCTION Base address TYPE RO/RW DESCRIPTION The size of this Base Address Register is defined from Upstream Memory 3 Upper 32-bit Setup Register (CSR Offset 038h), which can be initialized by EEPROM (I2C) or SM Bus or Local Processor. Writing a zero to bit [31] of the setup registers (CSR Offset 038h) to disable this register. This register defines the upper 32 bits of a memory range for upstream forwarding memory. PI7C9X110 uses this register and the Upstream Memory 3 Base Address Register when 64-bit addressing programmed (bit [21] of Offset 68h). When 64-bit addressing is disabled, no address translation is performed. All 64-bit address transactions on the secondary interface falling outside of the Downstream Memory 3 address range are forwarded upstream. Reset to 00000000h
7.5.41 EXPRESS TRANSMITTER/RECEIVER REGISTER - OFFSET 68h
BIT 1:0 FUNCTION Nominal Driver Current Control TYPE RW DESCRIPTION 00: 20mA 01: 10mA 10: 28mA 11: Reserved Reset to 00 0000: 1.00 x nominal driver current 0001: 1.05 x nominal driver current 0010: 1.10 x nominal driver current 0011: 1.15 x nominal driver current 0100: 1.20 x nominal driver current 0101: 1.25 x nominal driver current 0110: 1.30 x nominal driver current 0111: 1.35 x nominal driver current 1000: 1.60 x nominal driver current 1001: 1.65 x nominal driver current 1010: 1.70 x nominal driver current 1011: 1.75 x nominal driver current 1100: 1.80 x nominal driver current 1101: 1.85 x nominal driver current 1110: 1.90 x nominal driver current 1111: 1.95 x nominal driver current Reset to 0000 0000: 0.00 db 0001: -0.35 db 0010: -0.72 db 0011: -1.11 db 0100: -1.51 db 0101: -1.94 db 0110: -2.38 db 0111: -2.85 db 1000: -3.35 db 1001: -3.88 db 1010: -4.44 db 1011: -5.04 db 1100: -5.68 db 1101: -6.38 db 1110: -7.13 db 1111: -7.96 db Reset to 1000
5:2
Driver Current Scale Multiple Control
RW
11:8
Driver De-emphasis Level Control
RW
Page 93 of 145 Pericom Semiconductor November 2007, Revision 2.4
PI7C9X110
PCIe-to-PCI Reversible Bridge
BIT 13:12
FUNCTION Transmitter Termination Control
TYPE RW
DESCRIPTION 00: 52 ohms 01: 57 ohms 10: 43 ohms 11: 46 ohms Reset to 00 00: 52 ohms 01: 57 ohms 10: 43 ohms 11: 46 ohms Reset to 00
15:14
Receiver Termination Control
RW
7.5.42 MEMORY ADDRESS FORWARDING CONTROL REGISTER - OFFSET 68h
BIT 19:16 FUNCTION Lookup Table Page Size TYPE RW DESCRIPTION If bit [20] of Offset 68h is low, then 0000: Disable Upstream Memory 2 Base Address Register 0001: 256 bytes 0010: 512 bytes 0011: 1K bytes 0100: 2K bytes 0101: 4K bytes 0110: 8K bytes 0111: 16K bytes 1000: 32K bytes 1001: 64K bytes 1010: 128K bytes 1011: 256K bytes 1100: 512K bytes 1101: 1M bytes 1110: 2M bytes 1111: 4M bytes If bit [20] of Offset 68h is high, then 0000: Disable Upstream Memory 2 Base Address Register 0001: 8M bytes 0010: 16M bytes 0011: 32M bytes 01XX: Disable Upstream Memory 2 Base Address Register 1XXX: Disable Upstream Memory 2 Base Address Register Reset to 0h 0: Normal Lookup Table Page Size 1: Coarse Lookup Table Page Size Reset to 0 0: Any 64-bit address transactions on secondary interface falling outside of Downstream Memory 3 address range are forwarded upstream 1: Enable 64-bit address transaction forwarding upstream based on Upstream Memory 3 address range without address translation Reset to 0 Reset to 0
20
Lookup Table Page Size Extension
RW
21
Upstream 64-bit Address Range Enable
RW
29:22
Reserved
RO
Page 94 of 145 Pericom Semiconductor November 2007, Revision 2.4
PI7C9X110
PCIe-to-PCI Reversible Bridge
7.5.43 UPSTREAM MEMORY WRITE FRAGMENT CONTROL REGISTER - OFFSET 68h
BIT 31:30 FUNCTION Memory Write Fragment Control TYPE RW DESCRIPTION Upstream Memory Write Fragment Control 00: Fragment at 32-byte boundary 01: Fragment at 64-byte boundary 1x: Fragement at 128-byte boundary Reset to 10h
7.5.44 SUBSYSTEM VENDOR ID REGISTER - OFFSET 6Ch
BIT 15:0 FUNCTION Subsystem Vendor ID TYPE RO DESCRIPTION Subsystem vendor ID identifies the particular add-in card or subsystem. Reset to 00h
7.5.45 SUBSYSTEM ID REGISTER - OFFSET 6Ch
BIT 31:16 FUNCTION Subsystem ID TYPE RO DESCRIPTION Subsystem ID identifies the particular add-in card or subsystem. Reset to 00h
7.5.46 EEPROM AUTOLOAD CONTROL/STATUS REGISTER - OFFSET 70h
BIT 0 FUNCTION Initiate EEPROM Read or Write Cycle TYPE RW DESCRIPTION This bit will be reset to 0 after the EEPROM operation is finished. 0: EEPROM AUTOLOAD disabled 0 -> 1: Starts the EEPROM Read or Write cycle Reset to 0 0: Read 1: Write Reset to 0 0: EEPROM acknowledge is always received during the EEPROM cycle 1: EEPROM acknowledge is not received during EEPROM cycle Reset to 0 0: EEPROM autoload is not successfully completed 1: EEPROM autoload is successfully completed Reset to 0 Where PCLK is 125MHz 00: PCLK / 4096 01: PCLK / 2048 10: PCLK / 1024 11: PCLK / 128 Reset to 00 0: Enable EEPROM autoload 1: Disable EEPROM autoload Reset to 0
1
Control Command for EEPROM
RW
2
EEPROM Error
RO
3
EPROM Autoload Complete Status
RO
5:4
EEPROM Clock Frequency Control
RW
6
EEPROM Autoload Control
RW
Page 95 of 145 Pericom Semiconductor November 2007, Revision 2.4
PI7C9X110
PCIe-to-PCI Reversible Bridge
BIT 7
FUNCTION Fast EEPROM Autoload Control
TYPE RW
DESCRIPTION 0: Normal speed of EEPROM autoload 1: Increase EEPROM autoload by 32x Reset to 0 0: EEPROM autoload is not on going 1: EEPROM autoload is on going Reset to 0 EEPROM word address for EEPROM cycle Reset to 0000000 EEPROM data to be written into the EEPROM Reset to 0000h
8
EEPROM Autoload Status
RO
15:9
EEPROM Word Address
RW
31:16
EEPROM Data
RW
7.5.47 RESERVED REGISTER - OFFSET 74h 7.5.48 BRIDGE CONTROL AND STATUS REGISTER - OFFSET 78h
BIT 1:0 2 FUNCTION Reserved SERR_L Forward Enable TYPE RO RW/RO DESCRIPTION Reset to 00 0: Disable the forwarding of SERR_L to ERR_FATAL and ERR_NONFATAL 1: Enable the forwarding of SERR_L to ERR_FATAL and ERR_NONFATAL Reset to 0 (FORWARD BRIDGE) RO bit for REVERSE BRIDGE 0: Do not force the assertion of RESET_L on secondary PCI/PCI-X bus in forward bridge mode, or do not generate a hot reset on the PCI Express link in reverse bridge mode 1: Force the assertion of RESET_L on secondary PCI/PCI-X bus in forward bridge mode, or generate a hot reset on the PCI Express link in reverse bridge mode Reset to 0 00: VGA memory and I/O transactions on the primary and secondary interfaces are ignored, unless decoded by other mechanism 01: VGA memory and I/O transactions on the primary interface are forwarded to secondary interface without address translation, but VGA transactions on secondary interface are ignored 10: VGA memory and I/O transactions on the secondary interface are forwarded to primary interface without address translation, but VGA transactions on primary interface are ignored Reset to 00 0: Execute 10-bit address decodes on VGA I/O accesses 1: Execute 16-bit address decode on VGA I/O accesses Reset to 0 0: Do not report master aborts (return FFFFFFFFh on reads and discards data on write) 1: Report master abort by signaling target abort if possible or by the assertion of SERR_L (if enabled). Reset to 0 0: Primary discard timer counts 215 PCI clock cycles 1: Primary discard timer counts 210 PCI clock cycles FORWARD BRIDGE - Bit is RO and ignored by PI7C9X110 Reset to 0
3
Secondary Interface Reset
RW
5:4
VGA Enable
RW
6
VGA 16-bit Decode
RW
7
Master Abort Mode
RW
8
Primary Master Timeout
RW
Page 96 of 145 Pericom Semiconductor November 2007, Revision 2.4
PI7C9X110
PCIe-to-PCI Reversible Bridge
BIT 9
FUNCTION Secondary Master Timeout
TYPE RW
DESCRIPTION 0: Secondary discard timer counts 215 PCI clock cycles 1: Secondary discard timer counts 210 PCI clock cycles REVERSE BRIDGE - Bit is RO and ignored by PI7C9X110 Reset to 0 Bit is set when the discard timer expires and a delayed completion is discarded at the PCI interface for the forward or reverse bridge Reset to 0 Bit is set to enable to generate ERR_NONFATAL or ERR_FATAL for forward bridge, or assert SERR_L for reverse bridge as a result of the expiration of the discard timer. It has no meaning if PI7C9X110 is in PCI-X mode. Reset to 0
10
Master Timeout Status
RWC
11
Discard Timer SERR_L Enable
RW
7.5.49 GPIO DATA AND CONTROL REGISTER - OFFSET 78h
BIT 15:12 19:16 23:20 27:24 31:28 FUNCTION GPIO Output Write-1-toClear GPIO Output Write-1-to-Set GPIO Output Enable Write1-to-Clear GPIO Output Enable Write1-to-Set GPIO Input Data Register TYPE RW RW RW RW RO DESCRIPTION Reset to 0h Reset to 0h Reset to 0h Reset to 0h Reset to 0h
7.5.50 SECONDARY INTERRUPT LINE REGISTER - OFFSET 7Ch
BIT 7:0 FUNCTION Secondary Interrupt Line TYPE RW DESCRIPTION These bits apply to forward bridge only. For initialization code to program to tell which input of the interrupt controller the bridge's INTA_L in connected to. Reset to 00000000
7.5.51 SECONDARY INTERRUPT PIN REGISTER - OFFSET 7Ch
BIT 15:8 FUNCTION Secondary Interrupt Pin TYPE RO DESCRIPTION These bits apply to forward bridge only. 00000001: Designates interrupt pin INTA_L is used Reset to 00h when reverse mode or 01h when forward mode.
7.5.52 SECONDARY MINIMUM GRANT REGISTER - OFFSET 7Ch
BIT 23:16 FUNCTION Secondary Minimum Grant TYPE RO DESCRIPTION This register is valid only in forward bridge mode. It specifies how long of a burst period that PI7C9X110 needs on the secondary bus in the units of 1/4 microseconds. Reset to 0
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PI7C9X110
PCIe-to-PCI Reversible Bridge
7.5.53 SECONDARY MAXIMUM LATENCY TIMER REGISTER - OFFSET 7Ch
BIT 31:24 FUNCTION Secondary Maximum Latency Timer TYPE RO DESCRIPTION This register is valid only in forward bridge mode. It specifies how often that PI7C9X110 needs to gain access to the primary bus in units of 1/4 microseconds. Reset to 0
7.5.54 PCI-X CAPABILITY ID REGISTER - OFFSET 80h
BIT 7:0 FUNCTION PCI-X Capability ID TYPE RO DESCRIPTION PCI-X Capability ID Reset to 07h
7.5.55 NEXT CAPABILITY POINTER REGISTER - OFFSET 80h
BIT 15:8 FUNCTION Next Capability Pointer TYPE RO DESCRIPTION Point to power management Reset to 90h
7.5.56 PCI-X SECONDARY STATUS REGISTER - OFFSET 80h
BIT 16 FUNCTION 64-bit Device on Secondary Bus Interface 133MHz Capable TYPE RO DESCRIPTION 64-bit not supported Reset to 0 When this bit is 1, PI7C9X110 is 133MHz capable on its secondary bus interface Reset to 1 in forward bridge mode or 0 in reverse bridge mode This bit is a read-only and set to 0 in reverse bridge mode or is read-write in forward bridge mode When this is set to 1, a split completion has been discarded by PI7C9X110 at secondary bus because the requester did not accept the split completion transaction Reset to 0 This bit is set to 0 in forward bridge mode or is read-write in reverse bridge mode When this is set to 1, an unexpected split completion has been received with the requester ID equaled to the secondary bus number, device number, and function number at the PI7X9X110 secondary bus interface Reset to 0 When this bit is set to 1, a split completion has been terminated by PI7C9X110 with either a retry or disconnect at the next ADB due to the buffer full condition Reset to 0 When this bit is set to 1, a split request is delayed because PI7C9X110 is not able to forward the split request transaction to its secondary bus due to insufficient room within the limit specified in the split transaction commitment limit field of the downstream split transaction control register Reset to 0
17
RO
18
Split Completion Discarded
RO / RWC
19
Unexpected Split Completion
RWC
20
Split Completion Overrun
RWC
21
Split Request Delayed
RWC
Page 98 of 145 Pericom Semiconductor November 2007, Revision 2.4
PI7C9X110
PCIe-to-PCI Reversible Bridge
BIT 24:22
FUNCTION Secondary Clock Frequency
TYPE RO
DESCRIPTION These bits are only meaningful in forward bridge mode. In reverse bridge mode, all three bits are set to zero. 000: Conventional PCI mode (minimum clock period not applicable) 001: 66MHz (minimum clock period is 15ns) 010: 100 to 133MHz (minimum clock period is 7.5ns) 011: Reserved 1xx: Reserved Reset to 000 0000000
31:25
Reserved
RO
7.5.57 PCI-X BRIDGE STATUS REGISTER - OFFSET 84h
BIT 2:0 FUNCTION Function Number TYPE RO DESCRIPTION Function number (AD [10:8] of a type 0 configuration transaction) Reset to 000 Device number (AD [15:11] of a type 0 configuration transaction) is assigned to the PI7C9X110 by the connection of system hardware. Each time the PI7C9X110 is addressed by a configuration write transaction, the bridge updates this register with the contents of AD [15:11] of the address phase of the configuration transaction, regardless of which register in the PI7C9X110 is addressed by the transaction. The PI7C9X110 is addressed by a configuration write transaction if all of the following are true: * The transaction uses a configuration write command * IDSEL is asserted during the address phase * AD [1:0] are 00 (type o configuration transaction) * AD [10:8] of the configuration address contain the appropriate function number Reset to 11111 Additional address from which the contents of the primary bus number register on type 1 configuration space header is read. The PI7C9X110 uses the bus number, device number, and function number fields to create a completer ID when responding with a split completion to a read of an internal PI7C9X110 register. These fields are also used for cases when one interface is in conventional PCI mode and the other is in PCI-X mode. Reset to 11111111 64-bit not supported Reset to 0 When this bit is 1, PI7C9X110 is 133MHz capable on its primary bus interface Reset to 0 in forward bridge mode or 1 in reverse bridge mode This bit is a read-only and set to 0 in reverse bridge mode or is read-write in forward bridge mode When this is set to 1, a split completion has been discarded by PI7C9X110 at primary bus because the requester did not accept the split completion transaction Reset to 0 This bit is set to 0 in forward bridge mode or is read-write in reverse bridge mode When this is set to 1, an unexpected split completion has been received with the requester ID equaled to the primary bus number, device number, and function number at the PI7X9X110 primary bus interface Reset to 0
7:3
Device Number
RO
15:8
Bus Number
RO
16
64-bit Device on Primary Bus Interface 133MHz Capable
RO
17
RO
18
Split Completion Discarded
RO / RWC
19
Unexpected Split Completion
RWC
Page 99 of 145 Pericom Semiconductor November 2007, Revision 2.4
PI7C9X110
PCIe-to-PCI Reversible Bridge
BIT 20
FUNCTION Split Completion Overrun
TYPE RWC
DESCRIPTION When this bit is set to 1, a split completion has been terminated by PI7C9X110 with either a retry or disconnect at the next ADB due to the buffer full condition Reset to 0 When this bit is set to 1, a split request is delayed because PI7C9X110 is not able to forward the split request transaction to its primary bus due to insufficient room within the limit specified in the split transaction commitment limit field of the downstream split transaction control register Reset to 0 0000000000
21
Split Request Delayed
RWC
31:22
Reserved
RO
7.5.58 UPSTREAM SPLIT TRANSACTION REGISTER - OFFSET 88h
BIT 15:0 FUNCTION Upstream Split Transaction Capability TYPE RO DESCRIPTION Upstream Split Transaction Capability specifies the size of the buffer (in the unit of ADQs) to store split completions for memory read. It applies to the requesters on the secondary bus in addressing the completers on the primary bus. The 0010h value shows that the buffer has 16 ADQs or 2K bytes storage Reset to 0010h Upstream Split Transaction Commitment Limit indicates the cumulative sequence size of the commitment limit in units of ADQs. This field can be programmed to any value or equal to the content of the split capability field. For example, if the limit is set to FFFFh, PI7C9X110 is allowed to forward all split requests of any size regardless of the amount of buffer space available. The split transaction commitment limit is set to 0010h that is the same value as the split transaction capability. Reset to 0010h
31:16
Upstream Split Transaction Commitment Limit
RW
7.5.59 DOWNSTREAM SPLIT TRANSACTION REGISTER - OFFSET 8Ch
BIT 15:0 FUNCTION Downstream Split Transaction Capability TYPE RO DESCRIPTION Downstream Split Transaction Capability specifies the size of the buffer (in the unit of ADQs) to store split completions for memory read. It applies to the requesters on the primary bus in addressing the completers on the secondary bus. The 0010h value shows that the buffer has 16 ADQs or 2K bytes storage Reset to 0010h Downstream Split Transaction Commitment Limit indicates the cumulative sequence size of the commitment limit in units of ADQs. This field can be programmed to any value or equal to the content of the split capability field. For example, if the limit is set to FFFFh, PI7C9X110 is allowed to forward all split requests of any size regardless of the amount of buffer space available. The split transaction commitment limit is set to 0010h that is the same value as the split transaction capability. Reset to 0010h
31:16
Downstream Split Transaction Commitment Limit
RW
7.5.60 POWER MANAGEMENT ID REGISTER - OFFSET 90h
BIT 7:0 FUNCTION Power Management ID TYPE RO DESCRIPTION Power Management ID Register Reset to 01h
Page 100 of 145 Pericom Semiconductor November 2007, Revision 2.4
PI7C9X110
PCIe-to-PCI Reversible Bridge
7.5.61 NEXT CAPABILITY POINTER REGISTER - OFFSET 90h
BIT 15:8 FUNCTION Next Pointer TYPE RO DESCRIPTION Next pointer (point to Subsystem ID and Subsystem Vendor ID) Reset to A8h
7.5.62 POWER MANAGEMENT CAPABILITY REGISTER - OFFSET 90h
BIT 18:16 FUNCTION Version Number TYPE RO DESCRIPTION Version number that complies with revision 2.0 of the PCI Power Management Interface specification. Reset to 010 PME clock is not required for PME_L generation Reset to 0 Reset to 0 DSI - no special initialization of this function beyond the standard PCI configuration header is required following transition to the D0 un-initialized state Reset to 0 000: 0mA 001: 55mA 010: 100mA 011: 160mA 100: 220mA 101: 270mA 110: 320mA 111: 375mA Reset to 001 D1 power management is not supported Reset to 0 D2 power management is not supported Reset to 0 PME_L is supported in D3 cold, D3 hot, and D0 states. Reset to 11001
19
PME Clock
RO
20 21
Reserved Device Specific Initialization (DSI)
RO RO
24:22
AUX Current
RO
25
D1 Power Management
RO
26
D2 Power Management
RO
31:27
PME_L Support
RO
7.5.63 POWER MANAGEMENT CONTROL AND STATUS REGISTER - OFFSET 94h
BIT 1:0 FUNCTION Power State TYPE RW DESCRIPTION Power State is used to determine the current power state of PI7C9X110. If a non-implemented state is written to this register, PI7C9X110 will ignore the write data. When present state is D3 and changing to D0 state by programming this register, the power state change causes a device reset without activating the RESET_L of PCI/PCI-X bus interface 00: D0 state 01: D1 state not implemented 10: D2 state not implemented 11: D3 state Reset to 00 Reset to 000000
7:2
Reserved
RO
Page 101 of 145 Pericom Semiconductor November 2007, Revision 2.4
PI7C9X110
PCIe-to-PCI Reversible Bridge
BIT 8
FUNCTION PME Enable
TYPE RWS
DESCRIPTION 0: PME_L assertion is disabled 1: PME_L assertion is enabled Reset to 0 Data register is not implemented Reset to 0000 Data register is not implemented Reset to 00 PME_L is supported Reset to 0
12:9
Data Select
RO
14:13
Data Scale
RO
15
PME Status
RWCS
7.5.64 PCI-TO-PCI SUPPORT EXTENSION REGISTER - OFFSET 94h
BIT 21:16 22 FUNCTION Reserved B2/B3 Support TYPE RO RO DESCRIPTION Reset to 000000 0: B2 / B3 not support for D3hot Reset to 0 0: PCI Bus Power/Clock Disabled Reset to 0 Data register is not implemented Reset to 00h
23
PCI Bus Power/Clock Control Enable Data Register
RO
31:24
RO
7.5.65 DOWNSTREAM MEMORY 0 TRANSLATED BASE REGISTER - OFFSET 98h
BIT 11:0 31:12 FUNCTION Reserved Downstream Memory 0 Translated Base TYPE RO RW DESCRIPTION Reset to 000h Define the translated base address for downstream memory transactions whose initiator addresses fall into Downstream Memory 0 (above lower 4K boundary) address range. The number of bits that are used for translated base is determined by its setup register (offset 9Ch) Reset to 00000h
7.5.66 DOWNSTREAM MEMORY 0 SETUP REGISTER - OFFSET 9Ch
BIT 0 FUNCTION Type Selector TYPE RO DESCRIPTION 0: Memory space is requested Reset to 0 00: 32-bit address space 01: 64-bit address space Reset to 00 0: Non-prefetchable 1: Prefetchable Reset to 0 Reset to 00h 0: Set the corresponding bit in the Base Address Register to read only. 1: Set the corresponding bit in the Base Address Register to read/write in order to control the size of the address range. Reset to 7FFFFh
2:1
Address Type
RO (WS)
3
Prefetchable Control
RO (WS)
11:4 30:12
Reserved Base Address Register Size
RO RO (WS)
Page 102 of 145 Pericom Semiconductor November 2007, Revision 2.4
PI7C9X110
PCIe-to-PCI Reversible Bridge
BIT 31
FUNCTION Base Address Register Enable
TYPE RO (WS)
DESCRIPTION Always set to 1 when a bus master attempts to write a zero to this bit. PI7C9X110 returns bit [31:12] as FFFFFh (for 4KB size). Reset to 1
7.5.67 CAPABILITY ID REGISTER - OFFSET A0h
BIT 7:0 FUNCTION Capability ID TYPE RO DESCRIPTION Capability ID for Slot Identification. SI is off by default but can be turned on through EEPROM interface Reset to 04h
Page 103 of 145 Pericom Semiconductor November 2007, Revision 2.4
PI7C9X110
PCIe-to-PCI Reversible Bridge
7.5.68 NEXT POINTER REGISTER - OFFSET A0h
BIT 15:8 FUNCTION Next Pointer TYPE RO DESCRIPTION Next pointer - points to PCI Express capabilities register Reset to B0h
7.5.69 SLOT NUMBER REGISTER - OFFSET A0h
BIT 20:16 FUNCTION Expansion Slot Number TYPE RW DESCRIPTION Expansion slot number Reset to 00000 First in chassis Reset to 0 Reset to 00
21
First In Chassis
RW
23:22
Reserved
RO
7.5.70 CHASSIS NUMBER REGISTER - OFFSET A0h
BIT 31:24 FUNCTION Chassis Number TYPE RW DESCRIPTION Chassis number Reset to 00h
7.5.71 SECONDARY CLOCK AND CLKRUN CONTROL REGISTER - OFFSET A4h
BIT 1:0 FUNCTION S_CLKOUT0 Enable TYPE RW DESCRIPTION S_CLKOUT (Slot 0) Enable for forward bridge mode only 00: enable S_CLKOUT0 01: enable S_CLKOUT0 10: enable S_CLKOUT0 11: disable S_CLKOUT0 and driven LOW Reset to 00 S_CLKOUT (Slot 1) Enable for forward bridge mode only 00: enable S_CLKOUT1 01: enable S_CLKOUT1 10: enable S_CLKOUT1 11: disable S_CLKOUT1 and driven LOW Reset to 00 S_CLKOUT (Slot 2) Enable for forward bridge mode only 00: enable S_CLKOUT2 01: enable S_CLKOUT2 10: enable S_CLKOUT2 11: disable S_CLKOUT2 and driven LOW Reset to 00 S_CLKOUT (Slot 3) Enable for forward bridge mode only 00: enable S_CLKOUT3 01: enable S_CLKOUT3 10: enable S_CLKOUT3 11: disable S_CLKOUT3 and driven LOW Reset to 00
3:2
S_CLKOUT1 Enable
RW
5:4
S_CLKOUT2 Enable
RW
7:6
S_CLKOUT3 Enable
RW
Page 104 of 145 Pericom Semiconductor November 2007, Revision 2.4
PI7C9X110
PCIe-to-PCI Reversible Bridge
BIT 8
FUNCTION S_CLKOUT4 Enable
TYPE RW
DESCRIPTION S_CLKOUT (Device 1) Enable for forward bridge mode only 0: enable S_CLKOUT4 1: disable S_CLKOUT4 and driven LOW Reset to 0 S_CLKOUT (Device 2) Enable for forward bridge mode only 0: enable S_CLKOUT5 1: disable S_CLKOUT5 and driven LOW Reset to 0 S_CLKOUT (Device 3) Enable for forward bridge mode only 0: enable S_CLKOUT6 1: disable S_CLKOUT6 and driven LOW Reset to 0 S_CLKOUT (Device 4) Enable for forward bridge mode only 0: enable S_CLKOUT7 1: disable S_CLKOUT7 and driven LOW Reset to 0 S_CLKOUT (the bridge) Enable for forward bridge mode only 0: enable S_CLKOUT8 1: disable S_CLKOUT8 and driven LOW Reset to 0 Secondary clock stop status 0: secondary clock not stopped 1: secondary clock stopped Reset to 0 0: disable protocol 1: enable protocol Reset to 0 0: Stop the secondary clock only when bridge is at D3hot state 1: Stop the secondary clock whenever the secondary bus is idle and there are no requests from the primary bus Reset to 0 Reset to 0000h
9
S_CLKOUT5 Enable
RW
10
S_CLKOUT6 Enable
RW
11
S_CLKOUT7 Enable
RW
12
S_CLKOUT8 Enable
RW
13
Secondary Clock Stop Status
RO
14
Secondary Clkrun Protocol Enable
RW
15
Clkrun Mode
RW
31:16
Reserved
RO
7.5.72 DONWSTREAM I/O OR MEMORY 1 TRANSLATED BASE REGISTER - OFFSET A8h
BIT 5:0 31:6 FUNCTION Reserved Downstream I/O or Memory 1 Translated Base TYPE RO RW DESCRIPTION Reset to 000000 Define the translated base address for downstream I/O or memory transactions whose initiator addresses fall into Downstream I/O or Memory 1 address range. The number of bits that are used for translated base is determined by its setup register (offset ACh) Reset to 00000h
Page 105 of 145 Pericom Semiconductor November 2007, Revision 2.4
PI7C9X110
PCIe-to-PCI Reversible Bridge
7.5.73 DOWSTREAM I/O OR MEMORY 1 SETUP REGISTER - OFFSET ACh
BIT 0 FUNCTION Type Selector TYPE RO DESCRIPTION 0: Memory space is requested Reset to 0 00: 32-bit address space 01: 64-bit address space Reset to 00 0: Non-prefetchable 1: Prefetchable Reset to 0 Reset to 00 0: Set the corresponding bit in the Base Address Register to read only. 1: Set the corresponding bit in the Base Address Register to read/write in order to control the size of the address range. If memory space is selected, bit [11:6] should be set to zeros. Reset to 00000000h 0: Disable this Base Address Register 1: Enable this Base Address Register Reset to 0
2:1
Address Type
RO (WS)
3
Prefetchable Control
RO (WS)
5:4 30:6
Reserved Base Address Register Size
RO RO (WS)
31
Base Address Register Enable
RO (WS)
7.5.74 PCI EXPRESS CAPABILITY ID REGISTER - OFFSET B0h
BIT 7:0 FUNCTION PCI Express Capability ID TYPE RO DESCRIPTION PCI Express capability ID Reset to 10h
7.5.75 NEXT CAPABILITY POINTER REGISTER - OFFSET B0h
BIT 15:8 FUNCTION Next Item Pointer TYPE RO DESCRIPTION Next item pointer (points to VPD register) Reset to D8h
7.5.76 PCI EXPRESS CAPABILITY REGISTER - OFFSET B0h
BIT 19:16 23:20 FUNCTION Capability Version Device / Port Type TYPE RO RO DESCRIPTION Reset to 1h 0000: PCI Express endpoint device 0001: Legacy PCI Express endpoint device 0100: Root port of PCI Express root complex 0101: Upstream port of PCI Express switch 0110: Downstream port of PCI Express switch 0111: PCI Express to PCI bridge 1000: PCI to PCI Express bridge Others: Reserved Reset to 7h for Forward Bridge or 8h for Reverse Bridge Reset to 0 for Forward Bridge or 1 for Reverse Bridge Reset to 0h Reset to 0
24 29:25 31:30
Slot Implemented Interrupt Message Number Reserved
RO RO RO
Page 106 of 145 Pericom Semiconductor November 2007, Revision 2.4
PI7C9X110
PCIe-to-PCI Reversible Bridge
7.5.77 DEVICE CAPABILITY REGISTER - OFFSET B4h
BIT 2:0 FUNCTION Maximum Payload Size TYPE RO DESCRIPTION 000: 128 bytes 001: 256 bytes 010: 512 bytes 011: 1024 bytes 100: 2048 bytes 101: 4096 bytes 110: reserved 111: reserved Reset to 001 No phantom functions supported Reset to 00 8-bit tag field supported Reset to 1 Endpoint L0's acceptable latency 000: less than 64 ns 001: 64 - 128 ns 010: 128 - 256 ns 011: 256 - 512 ns 100: 512 ns - 1 us 101: 1 - 2 us 110: 2 - 4 us 111: more than 4 us Reset to 000 Endpoint L1's acceptable latency 000: less than 1 us 001: 1 - 2 us 010: 2 - 4 us 011: 4 - 8 us 100: 8 - 16 us 101: 16 - 32 us 110: 32 - 64 us 111: more than 64 us Reset to 000 0: If Hot Plug is disabled 1: If Hot Plug is enabled at Forward Bridge Reset to 0 when hot-plug is disabled or 1 when hot-plug is enabled through strapping. 0: If Hot Plug is disabled 1: If Hot Plug is enable at Forward Bridge Reset to 0 when hot-plug is disabled or 1 when hot-plug is enabled through strapping. 0: If Hot Plug is disabled 1: If Hot Plug is enable at Forward Bridge Reset to 0 when hot-plug is disabled or 1 when hot-plug is enabled through strapping. Reset to 000 These bits are set by the Set_Slot_Power_Limit message Reset to 00h
4:3
Phantom Functions
RO
5
8-bit Tag Field
RO
8:6
Endpoint L0's Latency
RO
11:9
Endpoint L1's Latency
RO
12
Attention Button Present
RO
13
Attention Indicator Present
RO
14
Power Indicator Present
RO
17:15 25:18
Reserved Captured Slot Power Limit Value
RO RO
Page 107 of 145 Pericom Semiconductor November 2007, Revision 2.4
PI7C9X110
PCIe-to-PCI Reversible Bridge
BIT 27:26
FUNCTION Captured Slot Power Limit Scale Reserved
TYPE RO
DESCRIPTION This value is set by the Set_Slot_Power_Limit message Reset to 00 Reset to 0h
31:28
RO
7.5.78 DEVICE CONTROL REGISTER - OFFSET B8h
BIT 0 1 2 3 4 7:5 FUNCTION Correctable Error Reporting Enable Non-Fatal Error Reporting Enable Fatal Error Reporting Enable Unsupported Request Reporting Enable Relaxed Ordering Enable Max Payload Size TYPE RW RW RW RW RO RW DESCRIPTION Reset to 0h Reset to 0h Reset to 0h Reset to 0h Relaxed Ordering disabled Reset to 0h This field sets the maximum TLP payload size for the PI7C9X110 000: 128 bytes 001: 256 bytes 010: 512 bytes 011:1024 bytes 100: 2048 bytes 101: 4096 bytes 110: reserved 111: reserved Reset to 000 Reset to 0 Phantom functions not supported Reset to 0 Auxiliary power PM not supported Reset to 0 Bridge never sets the No Snoop attribute in the transaction it initiates Reset to 0 This field sets the maximum Read Request Size for the device as a requester 000: 128 bytes 001: 256 bytes 010: 512 bytes 011: 1024 bytes 100: 2048 bytes 101: 4096 bytes 110: reserved 111: reserved Reset to 2h Reset to 0
8 9
Extended Tag Field Enable Phantom Functions Enable
RW RO
10
Auxiliary Power PM Enable
RO
11
No Snoop Enable
RO
14:12
Maximum Read Request Size
RW
15
Configuration Retry Enable
RW
7.5.79 DEVICE STATUS REGISTER - OFFSET B8h
BIT 16 17 18 19 20 FUNCTION Correctable Error Detected Non-Fatal Error Detected Fatal Error Detected Unsupported Request Detected AUX Power Detected TYPE RWC RWC RWC RWC RO DESCRIPTION Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 1
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BIT 21
FUNCTION Transaction Pending
TYPE RO
DESCRIPTION 0: No transaction is pending on transaction layer interface 1: Transaction is pending on transaction layer interface Reset to 0 Reset to 0000000000
31:22
Reserved
RO
7.5.80 LINK CAPABILITY REGISTER - OFFSET BCh
BIT 3:0 FUNCTION Maximum Link Speed TYPE RO DESCRIPTION Indicates the maximum speed of the Express link 0001: 2.5Gb/s link Reset to 1 Indicates the maximum width of the Express link (x1 at reset) 000000: reserved 000001: x1 000010: x2 000100: x4 001000: x8 001100: x12 010000: x16 100000: x32 Reset to 000001 This field indicates the level of Active State Power Management Support 00: reserved 01: L0's entry supported 10: reserved 11: L0's and L1's supported Reset to 11 Reset to 3h Reset to 0h Reset to 0h Reset to 00h
9:4
Maximum Link Width
RO
11:10
ASPM Support
RO
14:12 17:15 23:18 31:24
L0's Exit Latency L1's Exit Latency Reserved Port Number
RO RO RO RO
7.5.81 LINK CONTROL REGISTER - OFFSET C0h
BIT 1:0 FUNCTION ASPM Control TYPE RW DESCRIPTION This field controls the level of ASPM supported on the Express link 00: disabled 01: L0's entry enabled 10: L1's entry enabled 11: L0's and L1's entry enabled Reset to 00 Reset to 0 Read completion boundary not supported Reset to 0 RO for Forward Bridge Reset to 0 RO for Forward Bridge Reset to 0 Reset to 0
2 3
Reserved Read Completion Boundary (RCB) Link Disable
RO RO
4
RO / RW RO / RW RW
5
Retrain Link
6
Common Clock Configuration
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BIT 7 15:8
FUNCTION Extended Sync Reserved
TYPE RW RO
DESCRIPTION Reset to 0 Reset to 00h
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7.5.82 LINK STATUS REGISTER - OFFSET C0h
BIT 19:16 FUNCTION Link Speed TYPE RO DESCRIPTION This field indicates the negotiated speed of the Express link 001: 2.5Gb/s link Reset to 1h 000000: reserved 000001: x1 000010: x2 000100: x4 001000: x8 001100: x12 010000: x16 100000: x32 Reset to 000001 Reset to 0 Reset to 0 Reset to 1 Reset to 0
25:20
Negotiated Link Width
RO
26 27 28 31:29
Link Train Error Link Training Slot Clock Configuration Reserved
RO RO RO RO
7.5.83 SLOT CAPABILITY REGISTER - OFFSET C4h
BIT 0 FUNCTION Attention Button Present TYPE RO DESCRIPTION 0: If Hot Plug is disabled 1: If Hot Plug is enabled at reverse bridge Reset to 0 when hot-plug is disabled or 1 when hot-plug is enabled through strapping. Reset to 0 0: If Hot Plug is disabled 1: If Hot Plug is enabled at reverse bridge Reset to 0 when hot-plug is disabled or 1 when hot-plug is enabled through strapping. 0: If Hot Plug is disabled 1: If Hot Plug is enabled at reverse bridge Reset to 0 when hot-plug is disabled or 1 when hot-plug is enabled through strapping. 0: If Hot Plug is disabled 1: If Hot Plug is enabled at reverse bridge Reset to 0 when hot-plug is disabled or 1 when hot-plug is enabled through strapping. Reset to 0 0: If Hot Plug is disabled 1: If Hot Plug is enabled at reverse bridge Reset to 0 when hot-plug is disabled or 1 when hot-plug is enabled through strapping. Reset to 00h Reset to 00 Reset to 00 Reset to 0
1 2
Power Controller Present MRL Sensor Present
RO RO
3
Attention Indicator Present
RO
4
Power Indicator Present
RO
5 6
Hot Plug Surprise Hot Plug Capable
RO RO
14:7 16:15 18:17 31:19
Slot Power Limit Value Slot Power Limit Scale Reserved Physical Slot Number
RO RO RO RO
7.5.84 SLOT CONTROL REGISTER - OFFSET C8h
BIT FUNCTION TYPE DESCRIPTION
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BIT 0 1 2 3 4 5 7:6 9:8 10 15:11
FUNCTION Attention Button Present Enable Power Fault Detected Enable MRL Sensor Changed Enable Presence Detect Changed Enable Command Completed Interrupt Enable Hot Plug Interrupt Enable Attention Indicator Control Power Indicator Control Power Controller Control Reserved
TYPE RW RW RW RW RW RW RW RW RW RO
DESCRIPTION Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0
7.5.85 SLOT STATUS REGISTER - OFFSET C8h
BIT 16 17 18 19 20 21 22 31:23 FUNCTION Attention Button Pressed Power Fault Detected MRL Sensor Changed Presence Detect Changed Command Completed MRL Sensor State Presence Detect State Reserved TYPE RO RO RO RO RO RO RO RO DESCRIPTION Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0
7.5.86 XPIP CONFIGURATION REGISTER 0 - OFFSET CCh
BIT 0 1 2 3 FUNCTION Hot Reset Enable Loopback Function Enable Cross Link Function Enable Software Direct to Configuration State when in LTSSM state Internal Selection for Debug Mode Negotiate Lane Number of Times TS1 Number Counter Reserved LTSSM Enter L1 Timer Default Value TYPE RW RW RW RW DESCRIPTION Reset to 0 Reset to 0 Reset to 0 Reset to 0
4 7:5 12:8 15:13 31:16
RW RW RW RO RW
Reset to 0 Reset to 3h Reset to 10h Reset to 0 Reset to 0400h
7.5.87 XPIP CONFIGURATION REGISTER 1 - OFFSET D0h
BIT 9:0 15:10 31:16 FUNCTION L0's Lifetime Timer Reserved L1 Lifetime Timer TYPE RW RO RW DESCRIPTION Reset to 0 Reset to 0 Reset to 0
7.5.88 XPIP CONFIGURATION REGISTER 2 - OFFSET D4h
BIT 7:0 FUNCTION CDR Recovery Time (in the number of FTS order sets) L0's Exit to L0 Latency TYPE RW DESCRIPTION Reset to 54h A Fast Training Sequence order set composes of one K28.5 (COM) Symbol and three K28.1 Symbols. Reset to 2h
14:8
RW
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BIT 15 22:16 31:23
FUNCTION Reserved L1 Exit to L0 Latency Reserved
TYPE RO RW RO
DESCRIPTION Reset to 0 Reset to 19h Reset to 0
7.5.89 CAPABILITY ID REGISTER - OFFSET D8h
BIT 7:0 FUNCTION Capability ID for VPD Register TYPE RO DESCRIPTION Reset to 03h
7.5.90 NEXT POINTER REGISTER - OFFSET D8h
BIT 15:8 FUNCTION Next Pointer TYPE RO DESCRIPTION Next pointer (F0h, points to MSI capabilities) Reset to F0h
7.5.91 VPD REGISTER - OFFSET D8h
BIT 17:16 23:18 30:24 31 FUNCTION Reserved VPD Address for Read/Write Cycle Reserved VPD Operation TYPE RO RW RO RW DESCRIPTION Reset to 0 Reset to 0 Reset to 0 0: Generate a read cycle from the EEPROM at the VPD address specified in bits [7:2] of offset D8h. This bit remains at `0' until EEPROM cycle is finished, after which the bit is then set to `1'. Data for reads is available at register ECh. 1: Generate a write cycle to the EEPROM at the VPD address specified in bits [7:2] of offset D8h. This bit remains at `1' until EEPROM cycle is finished, after which it is then cleared to `0'. Reset to 0
7.5.92 VPD DATA REGISTER - OFFSET DCh
BIT 31:0 FUNCTION VPD Data TYPE RW DESCRIPTION VPD Data (EEPROM data [address + 0x40]) The least significant byte of this register corresponds to the byte of VPD at the address specified by the VPD address register. The data read form or written to this register uses the normal PCI byte transfer capabilities. Reset to 0
7.5.93 UPSTREAM MEMORY 0 TRANSLATED BASE REGISTER - OFFSET E0h
BIT 11:0 31:12 FUNCTION Reserved Downstream Memory 0 Translated Base TYPE RO RW DESCRIPTION Reset to 000h Define the translated base address for upstream memory transactions whose initiator addresses fall into Upstream Memory 0 (above lower 4K boundary) address range. The number of bits that are used for translated base is determined by its setup register (offset E4h) Reset to 00000h
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7.5.94 UPSTREAM MEMORY 0 SETUP REGISTER - OFFSET E4h
BIT 0 FUNCTION Type Selector TYPE RO DESCRIPTION 0: Memory space is requested Reset to 0 00: 32-bit address space 01: 64-bit address space Reset to 00 0: Non-prefetchable 1: Prefetchable Reset to 0 Reset to 00h 0: Set the corresponding bit in the Base Address Register to read only. 1: Set the corresponding bit in the Base Address Register to read/write in order to control the size of the address range. Reset to 00000h Always set to 1 when a bus master attempts to write a zero to this bit. PI7C9X110 returns bit [31:12] as FFFFFh (for 4KB size). Reset to 1
2:1
Address Type
RO (WS)
3
Prefetchable Control
RO (WS)
11:4 30:12
Reserved Base Address Register Size
RO RO (WS)
31
Base Address Register Enable
RO (WS)
7.5.95 UPSTREAM I/O OR MEMORY 1 TRANSLATED BASE REGISTER - OFFSET E8h
BIT 5:0 31:6 FUNCTION Reserved Upstream I/O or Memory 1 Translated Base TYPE RO RW DESCRIPTION Reset to 000000 Define the translated base address for upstream I/O or memory transactions whose initiator addresses fall into Upstream I/O or Memory 1 address range. The number of bits that are used for translated base is determined by its setup register (offset ECh) Reset to 00000h
7.5.96 UPSTREAM I/O OR MEMORY 1 SETUP REGISTER - OFFSET ECh
BIT 0 FUNCTION Type Selector TYPE RO DESCRIPTION 0: Memory space is requested Reset to 0 00: 32-bit address space 01: 64-bit address space Reset to 00 0: Non-prefetchable 1: Prefetchable Reset to 0 Reset to 00 0: Set the corresponding bit in the Base Address Register to read only. 1: Set the corresponding bit in the Base Address Register to read/write in order to control the size of the address range. If memory space is selected, bit [11:6] should be set to zeros. Reset to 00000000h
2:1
Address Type
RO (WS)
3
Prefetchable Control
RO (WS)
5:4 30:6
Reserved Base Address Register Size
RO RO (WS)
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BIT 31
FUNCTION Base Address Register Enable
TYPE RO (WS)
DESCRIPTION 0: Disable this Base Address Register 1: Enable this Base Address Register Reset to 0
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7.5.97 MESSAGE SIGNALED INTERRUPTS ID REGISTER - F0h
BIT 7:0 FUNCTION Capability ID for MSI Registers TYPE RO DESCRIPTION Reset to 05h
7.5.98 NEXT CAPABILITIES POINTER REGISTER - F0h
BIT 15:8 FUNCTION Next Pointer TYPE RO DESCRIPTION Next pointer (00h indicates the end of capabilities) Reset to 00h
7.5.99 MESSAGE CONTROL REGISTER - OFFSET F0h
BIT 16 FUNCTION MSI Enable TYPE RW DESCRIPTION 0: Disable MSI and default to INTx for interrupt 1: Enable MSI for interrupt service and ignore INTx interrupt pins 000: 1 message requested 001: 2 messages requested 010: 4 messages requested 011: 8 messages requested 100: 16 messages requested 101: 32 messages requested 110: reserved 111: reserved Reset to 000 000: 1 message requested 001: 2 messages requested 010: 4 messages requested 011: 8 messages requested 100: 16 messages requested 101: 32 messages requested 110: reserved 111: reserved Reset to 000 Reset to 1 Reset to 00h
19:17
Multiple Message Capable
RO
22:20
Multiple Message Enable
RW
23 31:24
64-bit Address Capable Reserved
RW RO
7.5.100 MESSAGE ADDRESS REGISTER - OFFSET F4h
BIT 1:0 31:2 FUNCTION Reserved System Specified Message Address TYPE RO RW DESCRIPTION Reset to 00 Reset to 0
7.5.101 MESSAGE UPPER ADDRESS REGISTER - OFFSET F8h
BIT 31:0 FUNCTION System Specified Message Upper Address TYPE RW DESCRIPTION Reset to 0
7.5.102 MESSAGE DATA REGISTER - OFFSET FCh
BIT FUNCTION TYPE DESCRIPTION
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BIT 15:0 31:16
FUNCTION System Specified Message Data Reserved
TYPE RW RO
DESCRIPTION Reset to 0 Reset to 0
7.5.103 ADVANCE ERROR REPORTING CAPABILITY ID REGISTER - OFFSET 100h
BIT 15:0 FUNCTION Advance Error Reporting Capability ID TYPE RO DESCRIPTION Reset to 0001h
7.5.104 ADVANCE ERROR REPORTING CAPABILITY VERSION REGISTER - OFFSET 100h
BIT 19:16 FUNCTION Advance Error Reporting Capability Version TYPE RO DESCRIPTION Reset to 1h
7.5.105 NEXT CAPABILITY OFFSET REGISTER - OFFSET 100h
BIT 31:20 FUNCTION Next Capability Offset TYPE RO DESCRIPTION Next capability offset (150h points to VC capability) Reset to 150h
7.5.106 UNCORRECTABLE ERROR STATUS REGISTER - OFFSET 104h
BIT 0 3:1 4 11:5 12 13 14 15 16 17 18 19 20 31:21 FUNCTION Training Error Status Reserved Data Link Protocol Error Status Reserved Poisoned TLP Status Flow Control Protocol Error Status Completion Timeout Status Completer Abort Status Unexpected Completion Status Receiver Overflow Status Malformed TLP Status ECRC Error Status Unsupported Request Error Status Reserved TYPE RWCS RO RWCS RO RWCS RWCS RWCS RWCS RWCS RWCS RWCS RWCS RWCS RO DESCRIPTION Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0
7.5.107 UNCORRECTABLE ERROR MASK REGISTER - OFFSET 108h
BIT 0 3:1 4 11:5 12 13 14 15 FUNCTION Training Error Mast Reserved Data Link Protocol Error Mask Reserved Poisoned TLP Mask Flow Control Protocol Error Mask Completion Timeout Mask Completion Abort Mask TYPE RWS RO RWS RO RWS RWS RWS RWS DESCRIPTION Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0
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BIT 16 17 18 19 20 31:21
FUNCTION Unexpected Completion Mask Receiver Overflow Mask Malformed TLP Mask ECRC Error Mask Unsupported Request Error Mask Reserved
TYPE RWS RWS RWS RWS RWS RO
DESCRIPTION Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0
7.5.108 UNCORRECTABLE ERROR SEVERITY REGISTER - OFFSET 10Ch
BIT 0 3:1 4 11:5 12 13 14 15 16 17 18 19 20 31:21 FUNCTION Training Error Severity Reserved Data Link Protocol Error Severity Reserved Poisoned TLP Severity Flow Control Protocol Error Severity Completion Timeout Severity Completer Abort Severity Unexpected Completion Severity Receiver Overflow Severity Malformed TLP Severity ECRC Error Severity Unsupported Request Error Severity Reserved TYPE RWS RO RWS RO RWS RWS RWS RWS RWS RWS RWS RWS RWS RO DESCRIPTION Reset to 1 Reset to 0 Reset to 1 Reset to 0 Reset to 0 Reset to 1 Reset to 0 Reset to 0 Reset to 0 Reset to 1 Reset to 1 Reset to 0 Reset to 0 Reset to 0
7.5.109 CORRECTABLE ERROR STATUS REGISTER - OFFSET 110h
BIT 0 5:1 6 7 8 11:9 12 31:13 FUNCTION Receiver Error Status Reserved Bad TLP Status Bad DLLP Status REPLAY_NUM Rollover Status Reserved Replay Timer Timeout Status Reserved TYPE RWCS RO RWCS RWCS RWCS RO RWCS RO DESCRIPTION Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0
7.5.110 CORRECTABLE ERROR MASK REGISTER - OFFSET 114h
BIT 0 5:1 6 7 8 11:9 12 31:13 FUNCTION Receiver Error Mask Reserved Bad TLP Mask Bad DLLP Mask REPLAY_NUM Rollover Mask Reserved Replay Timer Timeout Mask Reserved TYPE RWS RO RWS RWS RWS RO RWS RO DESCRIPTION Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0
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7.5.111 ADVANCED ERROR CAPABILITIES AND CONTROL REGISTER - OFFSET 118h
BIT 4:0 5 6 7 8 31:9 FUNCTION First Error Pointer ECRC Generation Capable ECRC Generation Enable ECRC Check Capable ECRC Check Enable Reserved TYPE ROS RO RWS RO RWS RO DESCRIPTION Reset to 0h Reset to 1 Reset to 0 Reset to 1 Reset to 0 Reset to 0
7.5.112 HEADER LOG REGISTER 1 - OFFSET 11Ch
BIT 7:0 15:8 23:16 31:24 FUNCTION Header Byte 3 Header Byte 2 Header Byte 1 Header Byte 0 TYPE ROS ROS ROS ROS DESCRIPTION Reset to 0 Reset to 0 Reset to 0 Reset to 0
7.5.113 HEADER LOG REGISTER 2 - OFFSET 120h
BIT 7:0 15:8 23:16 31:24 FUNCTION Header Byte 7 Header Byte 6 Header Byte 5 Header Byte 4 TYPE ROS ROS ROS ROS DESCRIPTION Reset to 0 Reset to 0 Reset to 0 Reset to 0
7.5.114 HEADER LOG REGISTER 3 - OFFSET 124h
BIT 7:0 15:8 23:16 31:24 FUNCTION Header Byte 11 Header Byte 10 Header Byte 9 Header Byte 8 TYPE ROS ROS ROS ROS DESCRIPTION Reset to 0 Reset to 0 Reset to 0 Reset to 0
7.5.115 HEADER LOG REGISTER 4 - OFFSET 128h
BIT 7:0 15:8 23:16 31:24 FUNCTION Header Byte 15 Header Byte 14 Header Byte 13 Header Byte 12 TYPE ROS ROS ROS ROS DESCRIPTION Reset to 0 Reset to 0 Reset to 0 Reset to 0
7.5.116 SECONDARY UNCORRECTABLE ERROR STATUS REGISTER - OFFSET 12Ch
BIT 0 1 2 3 4 5 FUNCTION Target Abort on Split Completion Status Master Abort on Split Completion Status Received Target Abort Status Received Master Abort Status Reserved Unexpected Split Completion Error Status TYPE RWCS RWCS RWCS RWCS RO RWCS DESCRIPTION Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0
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BIT 6
7 8 9 10 11 12 13 31:14
FUNCTION Uncorrectable Split Completion Message Data Error Status Uncorrectable Data Error Status Uncorrectable Attribute Error Status Uncorrectable Address Error Status Delayed Transaction Discard Timer Expired Status PERR_L Assertion Detected Status SERR_L Assertion Detected Status Internal Bridge Error Status Reserved
TYPE RWCS
DESCRIPTION Reset to 0
RWCS RWCS RWCS RWCS RWCS RWCS RWCS RO
Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0
7.5.117 SECONDARY UNCORRECTABLE ERROR MASK REGISTER - OFFSET 130h
BIT 0 1 2 3 4 5 6 FUNCTION Target Abort on Split Completion Mask Master Abort on Split Completion Mask Received Target Abort Mask Received Master Abort Mask Reserved Unexpected Split Completion Error Mask Uncorrectable Split Completion Message Data Error Mask Uncorrectable Data Error Mask Uncorrectable Attribute Error Mask Uncorrectable Address Error Mask Delayed Transaction Discard Timer Expired Mask PERR_L Assertion Detected Mask SERR_L Assertion Detected Mask Internal Bridge Error Mask Reserved TYPE RWS RWS RWS RWS RO RWS RWS DESCRIPTION Reset to 0 Reset to 0 Reset to 0 Reset to 1 Reset to 0 Reset to 1 Reset to 0
7 8 9 10 11 12 13 31:14
RWS RWS RWS RWS RWS RWS RWS RO
Reset to 1 Reset to 1 Reset to 1 Reset to 1 Reset to 0 Reset to 1 Reset to 0 Reset to 0
7.5.118 SECONDARY UNCORRECTABLE ERROR SEVERITY REGISTER - OFFSET 134h
BIT 0 1 2 3 4 FUNCTION Target Abort on Split Completion Severity Master Abort on Split Completion Severity Received Target Abort Severity Received Master Abort Severity Reserved TYPE RWS RWS RWS RWS RO DESCRIPTION Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0
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BIT 5 6
7 8 9 10 11 12 13 31:14
FUNCTION Unexpected Split Completion Error Severity Uncorrectable Split Completion Message Data Error Severity Uncorrectable Data Error Severity Uncorrectable Attribute Error Severity Uncorrectable Address Error Severity Delayed Transaction Discard Timer Expired Severity PERR_L Assertion Detected Severity SERR_L Assertion Detected Severity Internal Bridge Error Severity Reserved
TYPE RWS RWS
DESCRIPTION Reset to 0 Reset to 1
RWS RWS RWS RWS RWS RWS RWS RO
Reset to 0 Reset to 1 Reset to 1 Reset to 0 Reset to 0 Reset to 1 Reset to 0 Reset to 0
7.5.119 SECONDARY ERROR CAPABILITY AND CONTROL REGISTER - OFFSET 138h
BIT 4:0 31:5 FUNCTION Secondary First Error Pointer Reserved TYPE ROW RO DESCRIPTION Reset to 0 Reset to 0
7.5.120 SECONDARY HEADER LOG REGISTER - OFFSET 13Ch - 148h
BIT 35:0 FUNCTION Transaction Attribute TYPE ROS DESCRIPTION Transaction attribute, CBE [3:0] and AD [31:0] during attribute phase Reset to 0 Transaction command lower, CBE [3:0] during first address phase Reset to 0 Transaction command upper, CBE [3:0] during second address phase of DAC transaction Reset to 0 Reset to 0 Transaction address, AD [31:0] during first address phase Reset to 0 Transaction address, AD [31:0] during second address phase of DAC transaction Reset to 0
39:36
Transaction Command Lower Transaction Command Upper
ROS
43:40
ROS
63:44 95:64
Reserved Transaction Address
ROS ROS
127:96
Transaction Address
ROS
7.5.121 RESERVED REGISTER - OFFSET 14Ch 7.5.122 VC CAPABILITY ID REGISTER - OFFSET 150h
BIT 15:0 FUNCTION VC Capability ID TYPE RO DESCRIPTION Reset to 0002h
7.5.123 VC CAPABILITY VERSION REGISTER - OFFSET 150h
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BIT 19:16
FUNCTION VC Capability Version
TYPE RO
DESCRIPTION Reset to 1h
7.5.124 NEXT CAPABILITY OFFSET REGISTER - OFFSET 150h
BIT 31:20 FUNCTION Next Capability Offset TYPE RO DESCRIPTION Next capability offset - the end of capabilities Reset to 0
7.5.125 PORT VC CAPABILITY REGISTER 1 - OFFSET 154h
BIT 2:0 3 6:4 7 9:8 11:10 31:12 FUNCTION Extended VC Count Reserved Low Priority Extended VC Count Reserved Reference Clock Port Arbitration Table Entry Size Reserved TYPE RO RO RO RO RO RO RO DESCRIPTION Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0
7.5.126 PORT VC CAPABILITY REGISTER 2 - OFFSET 158h
BIT 7:0 23:8 31:24 FUNCTION VC Arbitration Capability Reserved VC Arbitration Table Offset TYPE RO RO RO DESCRIPTION Reset to 0 Reset to 0 Reset to 0
7.5.127 PORT VC CONTROL REGISTER - OFFSET 15Ch
BIT 0 3:1 15:4 FUNCTION Load VC Arbitration Table VC Arbitration Select Reserved TYPE RO RO RO DESCRIPTION Reset to 0 Reset to 0 Reset to 0
7.5.128 PORT VC STATUS REGISTER - OFFSET 15Ch
BIT 16 31:17 FUNCTION VC Arbitration Table Status Reserved TYPE RO RO DESCRIPTION Reset to 0 Reset to 0
7.5.129 VC0 RESOURCE CAPABILITY REGISTER - OFFSET 160h
BIT 7:0 13:8 14 15 22:16 23 31:24 FUNCTION Port Arbitration Capability Reserved Advanced Packet Switching Reject Snoop Transactions Maximum Time Slots Reserved Port Arbitration Table Offset TYPE RO RO RO RO RO RO RO DESCRIPTION Reset to 0 Reset to 0 Reset to 0 Reset to0 Reset to 0 Reset to 0 Reset to 0
7.5.130 VC0 RESOURCE CONTROL REGISTER - OFFSET 164h
BIT FUNCTION TYPE DESCRIPTION
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BIT 0 7:1 15:8 16 19:17 23:20 26:24 30:27 31
FUNCTION TC / VC Map TC / VC Map Reserved Load Port Arbitration Table Port Arbitration Select Reserved VC ID Reserved VC Enable
TYPE RO RW RO RO RO RO RO RO RO
DESCRIPTION For TC0 Reset to 1 For TC7 to TC1 Reset to 7Fh Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 1
7.5.131 VC0 RESOURCE STATUS REGISTER - OFFSET 168h
BIT 0 1 31:2 FUNCTION Port Arbitration Table 1 VC0 Negotiation Pending Reserved TYPE RO RO RO DESCRIPTION Reset to 0 Reset to 0 Reset to 0
7.5.132 RESERVED REGISTERS - OFFSET 16Ch - 300h 7.5.133 EXTRA GPI/GPO DATA AND CONTROL REGISTER - OFFSET 304h
BIT 3:0 7:4 11:8 15:12 19:16 31:20 FUNCTION Extra GPO Extra GPO Extra GPO enable Extra GPO enable Extra GPI Reserved TYPE RWC RWS RWC RWS RO RO DESCRIPTION GPO [3:0], write 1 to clear Reset to 0 GPO [3:0], write 1 to set Reset to 0 GPO [3:0] enable, write 1 to clear Reset to 0 GPO [3:0] enable, write 1 to set Reset to 0 Extra GPI [3:0] Data Register Reset to 0 Reset to 0
7.5.134 RESERVED REGISTERS - OFFSET 308h - 30Ch 7.5.135 REPLAY AND ACKNOWLEDGE LATENCY TIMERS - OFFSET 310h
BIT 11:0 12 15:13 29:16 30 31 FUNCTION Replay Timer Replay Timer Enable Reserved Acknowledge Latency Timer Acknowledge Latency Timer Enable Reserved TYPE RW RW RO RW RO RO DESCRIPTION Replay Timer Reset to 0 Replay Timer Enable Reset to 0 Reset to 0 Acknowledge Latency Timer Reset to 0 Acknowledge Latency Timer Enable Reset to 0 Reset to 0
7.5.136 RESERVED REGISTERS - OFFSET 314h - FFCh
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7.6
CONTROL AND STATUS REGISTERS FOR NON-TRANSPARENT BRIDGE MODE
Control and Status Registers (CSR's) can be accessed by Memory or I/O transactions from both primary and secondary ports. The CSR's are defined and to be used along with configuration registers (see previous section 7.5 for details) for non-transparent bridge operations.
Register Type RO ROS RW RWC RWS RWCS Descriptions Read Only Read Only and Sticky Read/Write Read/Write "1" to clear Read/Write and Sticky Read/Write "1" to clear and Sticky
7.6.1 7.6.2
RESERVED REGISTERS - OFFSET 000h TO 004h DOWNSTREAM MEMORY 2 TRANSLATED BASE REGISTER - OFFSET 008h
BIT 11:0 31:12 FUNCTION Reserved Downstream Memory 2 Translated Base TYPE RO RW DESCRIPTION Reset to 000h Define the translated base address for downstream memory transactions whose initiator addresses fall into Downstream Memory 2 address range. The number of bits that are used for translated base is determined by its setup register (offset 00Ch) Reset to 00000h
7.6.3
DOWNSTREAM MEMORY 2 SETUP REGISTER - OFFSET 00Ch
BIT 0 FUNCTION Type Selector TYPE RO DESCRIPTION 0: Memory space is requested Reset to 0 00: 32-bit address space 01: 64-bit address space Reset to 00 0: Non-prefetchable 1: Prefetchable Reset to 0 Reset to 00 0: Set the corresponding bit in the Base Address Register to read only 1: Set the corresponding bit in the Base Address Register to read/write in order to control the size of the address range Reset to 00000h 0: Disable this Base Address Register 1: Enable this Base Address Register Reset to 0
2:1
Address Type
RO (WS)
3
Prefetchable Control
RO (WS)
11:4 30:12
Reserved Base Address Register Size
RO RO (WS)
31
Base Address Register Enable
RO (WS)
7.6.4
DOWNSTREAM MEMORY 3 TRANSLATED BASE REGISTER - OFFSET 010h
BIT 11:0 FUNCTION Reserved TYPE RO DESCRIPTION Reset to 000000
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BIT 31:12
FUNCTION Downstream Memory 3 Translated Base
TYPE RW
DESCRIPTION Define the translated base address for downstream memory transactions whose initiator addresses fall into Downstream Memory 3 address range. The number of bits that are used for translated base is determined by its setup register (offset 014h) Reset to 00000h
7.6.5
DOWNSTREAM MEMORY 3 SETUP REGISTER - OFFSET 014h
BIT 0 FUNCTION Type Selector TYPE RO DESCRIPTION 0: Memory space is requested Reset to 0 00: 32-bit address space 01: 64-bit address space Reset to 00 0: Non-prefetchable 1: Prefetchable Reset to 0 Reset to 00 0: Set the corresponding bit in the Base Address Register to read only 1: Set the corresponding bit in the Base Address Register to read/write in order to control the size of the address range Reset to 00000h 0: Disable this Base Address Register 1: Enable this Base Address Register Reset to 0
2:1
Address Type
RO (WS)
3
Prefetchable Control
RO (WS)
11:4 30:12
Reserved Base Address Register Size
RO RO (WS)
31
Base Address Register Enable
RO (WS)
7.6.6
DOWNSTREAM MEMORY 3 UPPER 32-BIT SETUP REGISTER - OFFSET 018h
BIT 30:0 FUNCTION Base Address Register Size TYPE RW DESCRIPTION 0: Set the corresponding bit in the Upper 32-bit Base Address Register to read only 1: Set the corresponding bit in the Upper 32-bit Base Address Register to read/write in order to control the size of the address range Reset to 00000000h 0: Disable 64-bit Base Address Register 1: Enable 64-bit Base Address Register Reset to 0
31
Base Address Register Enable
RW)
7.6.7 7.6.8
RESERVED REGISTERS - OFFSET 01Ch TO 030h UPSTREAM MEMORY 3 SETUP REGISTER - OFFSET 34h
BIT 0 FUNCTION Type Selector TYPE RO DESCRIPTION 0: Memory space is requested Reset to 0 00: 32-bit address space 01: 64-bit address space Reset to 01
2:1
Address Type
RO
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PCIe-to-PCI Reversible Bridge
BIT 3
FUNCTION Prefetchable Control
TYPE RW
DESCRIPTION 0: Non-prefetchable 1: Prefetchable Reset to 0 Reset to 00 0: Set the corresponding bit in the Base Address Register to read only 1: Set the corresponding bit in the Base Address Register to read/write in order to control the size of the address range Reset to 00000h
11:4 31:12
Reserved Base Address Register Size
RO RW
7.6.9
UPSTREAM MEMORY 3 UPPER 32-BIT SETUP REGISTER - OFFSET 038h
BIT 30:0 FUNCTION Base Address Register Size TYPE RW DESCRIPTION 0: Set the corresponding bit in the Upper 32-bit Base Address Register to read only 1: Set the corresponding bit in the Upper 32-bit Base Address Register to read/write in order to control the size of the address range Reset to 00000000h 0: Disable 64-bit Base Address Register 1: Enable 64-bit Base Address Register Reset to 0
31
Base Address Register Enable
RW
7.6.10 RESERVED REGISTERS - OFFSET 03Ch TO 04Ch 7.6.11 LOOKUP TABLE OFFSET - OFFSET 050h
BIT 7:0 FUNCTION Lookup Table Offset TYPE RW DESCRIPTION This register contains the byte offset of the Lookup Table Entry to be accessed for upstream memory 2. The access is initiated when the lookup Table Data Register is accessed. This register should be written first before any Lookup Table Data access. Reset to 00h Reset to 0
31:8
Reserved
RO
7.6.12 LOOKUP TABLE DATA - OFFSET 054h
BIT 0 FUNCTION Valid TYPE RW DESCRIPTION 0: Invalid lookup 1: Valid lookup Reset to 0 Reset to 00 0: Memory address is non-prefetchable 1: Memory address is Reset to 0 Reset to 0h
2:1 3
Reserved Prefetchable
RO RW
7:4
Reserved
RO
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PCIe-to-PCI Reversible Bridge
BIT 24:8
FUNCTION Translated base or Reserved
TYPE RW/RO
DESCRIPTION Data written or read from the Lookup Table at the offset specified in the Lookup Table Offset Register. When writing to this register, the data value is written to the specified Lookup Table entry. When reading from this register, the data reflects the data value from the specified Lookup Table entry. The bit [24:8] is Translated Base Register bit when the lookup table size is set to 256B range. The bit [24:8] is reserved when the lookup table size is set to 32MB range (see PCI configuration offset 68h for nontransparent mode). Reset to 0 Data written or read from the Lookup Table at the offset specified in the Lookup Table Offset Register. When writing to this register, the data value is written to a specific Lookup Table entry (CSR offset 100h - 1FFh). When reading from this register, the data reflects the data value from the specific Lookup Table entry. Reset to 0
31:25
Translated Base
RW
7.6.13 UPSTREAM PAGE BOUNDARY IRQ 0 REQUEST REGISTER - OFFSET 058h
BIT 31:0 FUNCTION Upstream Page Boundary IRQ 0 TYPE RWC DESCRIPTION Each interrupt request bit is correspondent to a page entry in the lower half of the Upstream Memory 2 range. Bit [0] is for the first page, and bit [31] is for the 32nd page. PI7C9X110 sets the appropriate bit when it successfully transfers data to or from the imitator that addresses the last Double Word in a page. PI7C9X110 initiates an interrupt request on secondary interface when the interrupt request bit is set and the corresponding Upstream Page Boundary IRQ 0 Mask bit is reset. When forward bridge, PI7C9X110 asserts INTA_L or generates MSI on secondary bus (PCI interface). When reverse bridge, PI7C9X110 sends INTA_L assertion message or generates MSI on secondary interface (PCI Express). When writing a "1" to this register, it clears the corresponding interrupt request bit. Reset to 0
7.6.14 UPSTREAM PAGE BOUNDARY IRQ 1 REQUEST REGISTER - OFFSET 05Ch
BIT 31:0 FUNCTION Upstream Page Boundary IRQ 1 TYPE RWC DESCRIPTION Each interrupt request bit is correspondent to a page entry in the lower half of the Upstream Memory 2 range. Bit [0] is for the 33rd page, and bit [31] is for the 64th page. PI7C9X110 sets the appropriate bit when it successfully transfers data to or from the initiator that addresses the last Double Word in a page. PI7C9X110 initiates an interrupt request on secondary interface when the interrupt request bit is set and the corresponding Upstream Page Boundary IRQ 1 Mask bit is reset. When forward bridge, PI7C9X110 asserts INTA_L or generates MSI on secondary bus (PCI interface). When reverse bridge, PI7C9X110 sends INTA_L assertion message or generates MSI on secondary interface (PCI Express). When wrting a "1" to this register, it clears the corresponding interrupt request bit. Reset to 0
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PCIe-to-PCI Reversible Bridge
7.6.15 UPSTREAM PAGE BOUNDARY IRQ 0 MASK REGISTER - OFFSET 060h
BIT 31:0 FUNCTION Upstream Page Boundary IRQ 0 Mask TYPE RWC DESCRIPTION 0: PI7C9X110 can initiate an interrupt request when the correspondent request bit is set 1: PI7C9X110 cannot initiate any interrupt request even though the correspondent request bit is set Reset to FFFFFFFFh
7.6.16 UPSTREAM PAGE BOUNDARY IRQ 1 MASK REGISTER - OFFSET 064h
BIT 31:0 FUNCTION Upstream Page Boundary IRQ 1 Mask TYPE RWC DESCRIPTION 0: PI7C9X110 can initiate an interrupt request when the correspondent request bit is set 1: PI7C9X110 cannot initiate any interrupt request even though the correspondent request bit is set Reset to FFFFFFFFh
7.6.17 RESERVED REGISTER - OFFSET 068C 7.6.18 PRIMARY CLEAR IRQ REGISTER - OFFSET 070h
BIT 15:0 FUNCTION Primary Clear IRQ TYPE RWC DESCRIPTION When writing "1" to this register bit, it clears the correspondent interrupt request bit. When reading this register, it returns the interrupt request bit status: 0: It is not the bit that causes the interrupt request on primary interface 1: It is the bit that causes the interrupt request on primary interface
Reset to 0000h
7.6.19 SECONDARY CLEAR IRQ REGISTER - OFFSET 070h
BIT 31:16 FUNCTION Secondary Clear IRQ TYPE RWC DESCRIPTION When writing "1" to this register bit, it clears the correspondent interrupt request bit. When reading this register, it returns the interrupt request bit status: 0: It is not the bit that causes the interrupt request on secondary interface 1: It is the bit that causes the interrupt request on secondary interface
Reset to 0000h
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PCIe-to-PCI Reversible Bridge
7.6.20 PRIMARY SET IRQ REGISTER - OFFSET 074h
BIT 15:0 FUNCTION Primary Set IRQ TYPE RWS DESCRIPTION When writing "1" to this register bit, it set the correspondent interrupt request bit. When reading this register, it returns the interrupt request bit status: 0: It is not the bit that causes the interrupt request on primary interface 1: It is the bit that causes the interrupt request on primary interface
Reset to 0000h
7.6.21 SECONDARY SET IRQ REGISTER - OFFSET 074h
BIT 31:16 FUNCTION Secondary Set IRQ TYPE RWS DESCRIPTION When writing "1" to this register bit, it set the correspondent interrupt request bit. When reading this register, it returns the interrupt request bit status: 0: It is not the bit that causes the interrupt request on secondary interface 1: It is the bit that causes the interrupt request on secondary interface
Reset to 0000h
7.6.22 PRIMARY CLEAR IRQ MASK REGISTER - OFFSET 078h
BIT 15:0 FUNCTION Primary Clear IRQ Mask TYPE RWS DESCRIPTION When writing "1" to this register bit, it clears the correspondent interrupt request mask bit. When reading this register, it returns the primary Clear IRQ Mask bit status: 0: It allows to clear an interrupt request on primary interface 1: It does not allow to clear any interrupt request on primary interface Reset to FFFFh
7.6.23 SECONDARY CLEAR IRQ MASK REGISTER - OFFSET 078h
BIT 31:16 FUNCTION Secondary Clear IRQ Mask TYPE RWS DESCRIPTION When writing "1" to this register bit, it clears the correspondent interrupt request mask bit. When reading this register, it returns the Secondary Clear IRQ Mask bit status: 0: It allows to clear an interrupt request on secondary interface 1: It does not allow to clear any interrupt request on secondary interface Reset to FFFFh
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PCIe-to-PCI Reversible Bridge
7.6.24 PRIMARY SET IRQ MASK REGISTER - OFFSET 07Ch
BIT 15:0 FUNCTION Primary Set IRQ Mask TYPE RWS DESCRIPTION When writing "1" to this register bit, it set the correspondent interrupt request mask bit. When reading this register, it returns the Primary Set IRQ Mask bit status: 0: It allows to set an interrupt request on primary interface 1: It does not allow to set any interrupt request on primary interface
Reset to FFFFh
7.6.25 SECONDARY SET IRQ MASK REGISTER - OFFSET 07Ch
BIT 31:16 FUNCTION Secondary Set IRQ Mask TYPE RWC DESCRIPTION When writing "1" to this register bit, it set the correspondent interrupt request mask bit. When reading this register, it returns the Secondary Set IRQ Mask bit status: 0: It allows to set an interrupt request on secondary interface 1: It does not allow to set any interrupt request on secondary interface Reset to FFFFh
7.6.26 RESERVED REGISTERS - OFFSET 080h TO 09Ch 7.6.27 SCRATCHPAD 0 REGISTER - OFFSET 0A0h
BIT 31:0 FUNCTION Scratchpad 0 TYPE RW DESCRIPTION The scratchpad is a 32-bit internal register that can be accessed from both primary and secondary interfaces. The external devices can use the scratchpad as a temporary storage. Primary and secondary bus devices can communicate through the scratchpad. However, writing and reading the scratchpad does not generate any interrupt request. Reset to 00000000h
7.6.28 SCRATCHPAD 1 REGISTER - OFFSET 0A4h
BIT 31:0 FUNCTION Scratchpad 1 TYPE RW DESCRIPTION The scratchpad is a 32-bit internal register that can be accessed from both primary and secondary interfaces. The external devices can use the scratchpad as a temporary storage. Primary and secondary bus devices can communicate through the scratchpad. However, writing and reading the scratchpad does not generate any interrupt request. Reset to 00000000h
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7.6.29 SCRATCHPAD 2 REGISTER - OFFSET 0A8h
BIT 31:0 FUNCTION Scratchpad 2 TYPE RW DESCRIPTION The scratchpad is a 32-bit internal register that can be accessed from both primary and secondary interfaces. The external devices can use the scratchpad as a temporary storage. Primary and secondary bus devices can communicate through the scratchpad. However, writing and reading the scratchpad does not generate any interrupt request. Reset to 00000000h
7.6.30 SCRATCHPAD 3 REGISTER - OFFSET 0ACh
BIT 31:0 FUNCTION Scratchpad 3 TYPE RW DESCRIPTION The scratchpad is a 32-bit internal register that can be accessed from both primary and secondary interfaces. The external devices can use the scratchpad as a temporary storage. Primary and secondary bus devices can communicate through the scratchpad. However, writing and reading the scratchpad does not generate any interrupt request. Reset to 00000000h
7.6.31 SCRATCHPAD 4 REGISTER - OFFSET 0B0h
BIT 31:0 FUNCTION Scratchpad 4 TYPE RW DESCRIPTION The scratchpad is a 32-bit internal register that can be accessed from both primary and secondary interfaces. The external devices can use the scratchpad as a temporary storage. Primary and secondary bus devices can communicate through the scratchpad. However, writing and reading the scratchpad does not generate any interrupt request. Reset to 00000000h
7.6.32 SCRATCHPAD 5 REGISTER - OFFSET 0B4h
BIT 31:0 FUNCTION Scratchpad 5 TYPE RW DESCRIPTION The scratchpad is a 32-bit internal register that can be accessed from both primary and secondary interfaces. The external devices can use the scratchpad as a temporary storage. Primary and secondary bus devices can communicate through the scratchpad. However, writing and reading the scratchpad does not generate any interrupt request. Reset to 00000000h
7.6.33 SCRATCHPAD 6 REGISTER - OFFSET 0B8h
BIT 31:0 FUNCTION Scratchpad 6 TYPE RW DESCRIPTION The scratchpad is a 32-bit internal register that can be accessed from both primary and secondary interfaces. The external devices can use the scratchpad as a temporary storage. Primary and secondary bus devices can communicate through the scratchpad. However, writing and reading the scratchpad does not generate any interrupt request. Reset to 00000000h
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7.6.34 SCRATCHPAD 7 REGISTER - OFFSET 0BCh
BIT 31:0 FUNCTION Scratchpad 7 TYPE RW DESCRIPTION The scratchpad is a 32-bit internal register that can be accessed from both primary and secondary interfaces. The external devices can use the scratchpad as a temporary storage. Primary and secondary bus devices can communicate through the scratchpad. However, writing and reading the scratchpad does not generate any interrupt request. Reset to 00000000h
7.6.35 RESERVED REGISTERS - OFFSET 0C0h TO 0FCh 7.6.36 LOOKUP TABLE REGISTERS - OFFSET 100h TO 1FCh
BIT 2047:0 FUNCTION Lookup Table TYPE RW DESCRIPTION The lookup table has 64 entries. Each entry has 32-bit mapped to each page of the Upstream Memory 2 base address range 64th page: bit [2047:2016] 62nd page: bit [1983:1952] 60th page: bit [1919:1888] 58th page: bit [1855:1824] 56th page: bit [1791:1760] 54th page: bit [1727:1696] 52nd page: bit [1663:1632] 50th page: bit [1599:1568] 48th page: bit [1535:1504] 46th page: bit [1471:1440] 44th page: bit [1407:1376] 42nd page: bit [1343:1312] 40th page: bit [1279:1248] 38th page: bit [1215:1184] 36th page: bit [1151:1120] 34th page: bit [1087:1056] 32nd page: bit [1023:992] 30th page: bit [959:928] 28th page: bit [895:864] 26th page: bit [831:800] 24th page: bit [767:736] 22nd page: bit [703:672] 20th page: bit [639:608] 18th page: bit [575:544] 16th page: bit [511:480] 14th page: bit [447:416] 12th page: bit [382:352] 10th page: bit [319:288] 8th page: bit [255:224] 6th page: bit [191:160] 4th page: bit [127:96] 2nd page: bit [63:32] Reset to unknown 63rd page: bit [2015:1984] 61st page: bit [1951:1920] 59th page: bit [1887:1856] 57th page: bit [1823:1792] 55th page: bit [1759:1728] 53rd page: bit [1695:1664] 51st page: bit [1631:1600] 49th page: bit [1567:1536] 47th page: bit [1503:1472] 45th page: bit [1439:1408] 43rd page: bit [1375:1344] 41st page: bit [1311:1280] 39th page: bit [1247:1216] 37th page: bit [1183:1152] 35th page: bit [1119:1088] 33rd page: bit [1055:1024] 31st page: bit [991:960] 29th page: bit [927:896] 27th page: bit [863:832] 25th page: bit [799:768] 23rd page: bit [735:704] 21st page: bit [671:640] 19th page: bit [607:576] 17th page: bit [543:512] 15th page: bit [479:448] 13th page: bit [415:383] 11th page: bit [351:320] 9th page: bit [287:256] 7th page: bit [223:192] 5th page: bit [159:128] 3rd page: bit [95:64] 1st page: bit [31:0]
7.6.37 RESERVED REGISTERS - OFFSET 200h TO FFCh
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8
GPIO PINS AND SM BUS ADDRESS
GPIO [3:1] of PI7C9X110 are defined for hot-plug usage if MSK_IN=1 during Reset. Please see configuration register definition (offset 78h - 7Bh). GPIO [3:0] are also defined the address bits of SMBUS device ID if SM Bus is selected (TM1=1). The addressstrapping table of SMBUS with GPIO [3:0] pins is defined in the following table: Table 8-1 SM Bus Device ID Strapping
SM Bus Address Bit Address bit [7] Address bit [6] Address bit [5] Address bit [4] Address bit [3] Address bit [2] Address bit [1] SM Bus device ID =1 =1 =0 = GPIO [3] = GPIO [2] = GPIO [1] = GPIO [0]
GPIO [3:0] pins can be further defined to serve other functions in the next generation Device. Four GPI [3:0] and four GPO [3:0] have been added to PI7C9X110 when external arbiter is selected (CFN_L=1). If external arbiter is selected, REQ_L [5:2] and GNT [5:2] will become the GPI [3:0] and GPO [3:0] respectively.
9
CLOCK SCHEME
PCI Express interface: PI7C9X110 requires 100MHz differential clock inputs through REFCLKP and REFCLKN Pins. PCI-X interface: PI7C9X110 requires PCI-X clock (up to 133MHz) to be connected to the CLKIN. PI7C9X110 uses the CLKIN and generates nine clock outputs, CLKOUT [8:0]. Also, PI7C9X110 requires one of the CLKOUT [8:0] (preferably CLKOUT [8]) to be connected to FBCLKIN for the PCI-X interface logic of PI7C9X110. The actual number of masters supported will vary depending on the loading of the PCI-X bus. Typically, PI7C9X110 can support up to one 133MHz PCI-X slot or two 66MHz PCI-X slots. PCI interface: PI7C9X110 requires PCI clock (up to 66MHz) to be connected to the CLKIN. PI7C9X110 uses the CLKIN and generates nine clock outputs, CLKOUT [8:0]. Also, PI7C9X110 requires one of the CLKOUT [8:0] (preferably CLKOUT [8]) to be connected to FBCLKIN for the PCI interface logic of PI7C9X110. The actual number of masters supported will vary depending on the loading of the PCI bus. Typically, PI7C9X110 can support up to four 66MHz PCI slots or eight 33MHz PCI slots. The PI7C9X110 PCI Clock Outputs, CLKOUT [8:0], can be enabled or disabled through the configuration register.
10
INTERRUPTS
PI7C9X110 supports interrupt message packets on PCIe side. PI7C9X110 supports PCI interrupt (INTA, B, C, D) pins or MSI (Message Signaled Interrupts) on PCI side. PCI interrupts and MSI are mutually exclusive. In order words, if MSI is enabled, PCI interrupts will be disabled. PI7C9X110 support 64-bit addressing MSI.
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PCIe-to-PCI Reversible Bridge
In reverse bridge mode, PI7C9X110 maps the interrupt message packets to PCI interrupt pins or MSI if MSI is enable (see configuration register bit [16] of Offset F0h). In forward bridge mode, PI7C9X110 maps the PCI interrupts pins or MSI if enable on PCI side to interrupt message packets on PCIe side. There are eight interrupt message packets. They are Assert_INTA, Assert_INTB, Assert_INTC, Assert_INTD, Deassert_INTA, Deassert_INTB, Deassert_INTC, and Deassert_INTD. These eight interrupt messages are mapped to the four PCI interrupts (INTA, INTB, INTC, and INTD). See Table 10-1 for interrupt mapping information in reverse bridge mode. PI7C9X110 tracks the PCI interrupt (INTA, INTB, INTC, and INTD) pins and maps them to the eight interrupt messages. See Table 10-2 for interrupt mapping information in forward bridge mode. Table 10-1 PCIe interrupt message to PCI interrupt mapping in reverse bridge mode
PCIe Interrupt messages (from sources of interrupt) INTA message INTB message INTC message INTD message PCI Interrupts (to host controller) INTA INTB INTC INTD
Table 10-2 PCI interrupt to PCIe interrupt message mapping in forward bridge mode
PCI Interrupts (from sources of interrupts) INTA INTB INTC INTD PCIe Interrupt message packets (to host controller) INTA message INTB message INTC message INTD message
11
EEPROM (I2C) INTERFACE AND SYSTEM MANAGEMENT BUS
11.1 EEPROM (I2C) INTERFACE
PI7C9X110 supports EEPROM interface through I2C bus. In EEPROM interface, pin A2 is the EEPROM clock (SCL) and pin A1 is the EEPROM data (SDL). When TM2 is strapped to low, TM1 selects EEPROM interface or System Management Bus. To select EEPROM (I2C) interface, TM1 needs to be set to low. When EEPROM interface is selected, SCL is an output. SCL is the I2C bus clock to the I2C device. In addition, SDL is a bidirectional signal for sending and receiving data.
11.2 SYSTEM MANAGEMENT BUS
PI7C9X110 supports SM bus protocol if TM1=1 when TM2 is strapped to low. In addition, SMBCLK (pin A2) and SMBDAT (pin A1) are utilized as the clock and data pins respectively for the SM bus. When SM bus interface is selected, SMBCLK pin is an input for the clock of SM bus and SMBDAT pin is an open drain buffer that requires external pull-up resistor for proper operation.
12
HOT PLUG OPERATION
PI7C9X110 is not equipped with standard hot-plug controller (SHPC) integrated. However, PI7C9X110 supports hot-plug signaling messages and registers to simplify the implementation of hot-plug system.
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PCIe-to-PCI Reversible Bridge
Using PI7C9X110 on motherboard: * * PI7C9X110 supports hot-plug on PCI bus if forward bridging is selected (REVRSB=0). PI7C9X110 supports hot-plug function on PCI Express bus when reverse bridge mode is selected (REVRSB=1).
Using PI7C9X110 on add-in card: * * PI7C9X110 supports hot-plug on PCI Express bus in forward bridge mode. Hot-plug messages will be generated by PI7C9X110 based on the add-in card conditions. PI7C9X110 supports hot-plug function on PCI bus when reverse bridge mode is selected. PI7C9X110 will tri-state the PCI bus when RESET is asserted. Also, PI7C9X110 will de-assert INTA_L if RESET is asserted. The state machine of PI7C9X110 PCI bus interface will remain idle if the RESET is asserted. After RESET is de-asserted, PI7C9X110 will remain in idle state until an address phase containing a valid address for PI7C9X110 or its downstream devices. PI7C9X110 expects the REFCLK signal will be provided to its upstream PCI Express Port prior to the deassertion of RESET. The Downstream PCI Port of PI7C9X110 supports a range of frequency up to 66MHz. PI7C9X110 also supports subsystem vendor and subsystem ID. PI7C9X110 will ignore target response while the bus is idle.
* *
PRSNT1# and PRSNT2# are not implemented on both PI7C9X110. The use of these two signals is mandatory on an add-in card in order to support hot-plug.
13
RESET SCHEME
PI7C9X110 requires the fundamental reset (PERST_L) input for internal logic when it is set as forward bridge mode. PI7C9X110 requires the PCI/PCI-X reset (RESET_L) input when it is set as reverse bridge mode. Also, PI7C9X110 has a power-on-reset (POR) circuit to detect VDDCAUX power supply for auxiliary logic control. * Cold Reset: A cold reset is a fundamental or power-on reset that occurs right after the power is applied to PI7C9X110 (during initial power up). See section 7.1.1 of PCI Express to PCI/PCI-X Bridge Specification, Revision 1.0 for details. * Warm Reset: A warm reset is a reset that triggered by the hardware without removing and re-applying the power sources to PI7C9X110. * Hot Reset: A hot reset is a reset that used an in-band mechanism for propagating reset across a PCIe link to PI7C9X110. PI7C9X110 will enter to training control reset when it receives two consecutive TS1 or TS2 order-sets with reset bit set. * DL_DOWN Reset: If the PCIe link goes down, the Transaction and Data Link Layer will enter DL_DOWN status. PI7C9X110 discards all transactions and returns all logic and registers to initial state except the sticky registers. Upon receiving reset (cold, warm, hot, or DL_DOWN) on PCIe interface, PI7C9X110 will generate PCI/PCI-X reset (RESET_L) to the downstream devices on the PCI/PCI-X bus in forward bridge mode. The PCI/PCI-X reset de-assertion follows the de-assertion of the reset received from PCIe interface. The reset bit of Bridge Control Register may be set depending on the application. PI7C9X110 will tolerant to receive and process SKIP order-sets
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at an average interval between 1180 to 1538 Symbol Times. PI7C9X110 does not keep PCI/PCI-X reset active when VD33 power is off even though VAUX (3.3v) is supported. It is recommended to add a weak pull-down resistor on its application board to ensure PCI/PCI-X reset is low when VD33 power is off (see section 7.3.2 of PCI Bus Power management Specification Revision 1.1). In reverse bridge mode, PI7C9X110 generates fundamental reset (PERST_L) and then 1024 TS1 order-sets with reset bit set when PCI/PCI-X reset (RESET_L) is asserted to PI7C9X110. PI7C9X110 has scheduling skip orderset for insertion at an interval between 1180 and 1538 Symbol Times. PI7C9X110 transmits one Electrical Idle order-set and enters to Electrical Idle.
14
IEEE 1149.1 COMPATIBLE JTAG CONTROLLER
An IEEE 1149.1 compatible Test Access Port (TAP) controller and associated TAP pins are provided to support boundary scan in PI7C9X110 for board-level continuity test and diagnostics. The TAP pins assigned are TCK, TDI, TDO, TMS and TRST_L. All digital input, output, input/output pins are tested except TAP pins. The IEEE 1149.1 Test Logic consists of a TAP controller, an instruction register, and a group of test data registers including Bypass and Boundary Scan registers. The TAP controller is a synchronous 16-state machine driven by the Test Clock (TCK) and the Test Mode Select (TMS) pins. An independent power on reset circuit is provided to ensure the machine is in TEST_LOGIC_RESET state at power-up. The JTAG signal lines are not active when the PCI resource is operating PCI bus cycles.
14.1 INSTRUCTION REGISTER
PI7C9X110 implements a 5-bit Instruction register to control the operation of the JTAG logic. The defined instruction codes are shown in Table 14-1. Those bit combinations that are not listed are equivalent to the BYPASS (11111) instruction: Table 14-1 Instruction register codes
Instruction EXTEST SAMPLE HIGHZ CLAMP IDCODE BYPASS INT_SCAN MEM_BIST Operation Code (binary) 00000 00001 00101 00100 01100 11111 00010 01010 Register Selected Boundary Scan Boundary Scan Bypass Bypass Device ID Bypass Internal Scan Memory BIST Operation Drives / receives off-chip test data Samples inputs / pre-loads outputs Tri-states output and I/O pins except TDO pin Drives pins from boundary-scan register and selects Bypass register for shifts Accesses the Device ID register, to read manufacturer ID, part number, and version number Selected Bypass Register Scan test Memory BIST test
14.2 BYPASS REGISTER
The required bypass register (one-bit shift register) provides the shortest path between TDI and TDO when a bypass instruction is in effect. This allows rapid movement of test data to and from other components on the board. This path can be selected when no test operation is being performed on the PI7C9X110.
14.3 DEVICE ID REGISTER
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This register identifies Pericom as the manufacturer of the device and details the part number and revision number for the device. Table 14-2 JTAG device ID register
Bit 31:28 27:12 11:1 0 Type RO RO RO RO Value 01h E110h 23Fh 1b Description Version number Last 4 digits (hex) of the die part number Pericom identifier assigned by JEDEC Fixed bit equal to 1'b1
14.4 BOUNDARY SCAN REGISTER
The boundary scan register has a set of serial shift-register cells. A chain of boundary scan cells is formed by connected the internal signal of the PI7C9X110 package pins. The VDD, VSS, and JTAG pins are not in the boundary scan chain. The input to the shift register is TDI and the output from the shift register is TDO. There are 4 different types of boundary scan cells, based on the function of each signal pin. The boundary scan register cells are dedicated logic and do not have any system function. Data may be loaded into the boundary scan register master cells from the device input pins and output pin-drivers in parallel by the mandatory SAMPLE and EXTEST instructions. Parallel loading takes place on the rising edge of TCK.
14.5 JTAG BOUNDARY SCAN REGISTER ORDER
Table 14-3 JTAG boundary scar register definition
Boundary Scan Register Number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Pin Name AD [0] AD [1] AD [2] AD [3] AD [4] AD [5] AD [6] AD [7] CBE [0] AD [8] AD [9] AD [10] AD [11] AD [12] AD [13] Ball Location K14 J11 J13 J14 H12 H13 G11 G12 G14 F11 F13 F14 E13 D11 D12 Type BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR Tri-state Control Cell 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29
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PI7C9X110
PCIe-to-PCI Reversible Bridge
Boundary Scan Register Number 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88
Pin Name AD [14] AD [15] CBE [1] PAR SERR_L PERR_L LOCK_L STOP_L DEVSEL_L TRDY_L IRDY_L FRAME_L CBE [2] AD [16] AD [17] AD [18] AD [19] AD [20] AD [21] AD [22] AD [23] CBE [3] AD [24] AD [25] AD [26] AD [27] AD [28] AD [29] AD [30] AD [31] -
Ball Location D14 C12 C14 B13 B14 A14 A13 A12 B11 A11 D10 B10 A10 C9 B9 D8 C8 A8 D7 B7 A7 C6 B6 D5 C5 A5 D4 B4 A4 B3 -
Type CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL
Tri-state Control Cell 31 33 35 37 39 41 43 45 47 47 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 -
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PI7C9X110
PCIe-to-PCI Reversible Bridge
Boundary Scan Register Number 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148
Pin Name PME_L SMBCLK SMBDAT CLKRUN_L FBCLKIN PCIXCAP PCIXUP PERST_L REQ_L [0] REQ_L [1] REQ_L [2] REQ_L [3] REQ_L [4] REQ_L [5] REQ_L [6] REQ_L [7] INTA_L GNT_L [0] GNT_L [1] GNT_L [2] GNT_L [3] GNT_L [4] GNT_L [5] GNT_L [6] GNT_L [7] INTB_L CLKIN RESET_L CFN_L GPIO [3] GPIO [2] GPIO [1] GPIO [0] CLKOUT [0] CLKOUT [1] CLKOUT [2] CLKOUT [3] CLKOUT [4] CLKOUT [5] CLKOUT [6] CLKOUT [7] CLKOUT [8] INTC_L -
Ball Location A3 A2 A1 D3 C2 B1 D2 L3 M1 M2 M3 N1 N2 N3 P1 P2 P3 M4 N4 L5 M5 N5 P5 P6 N6 M6 P7 N7 M7 L7 P8 M8 L8 P9 N9 L9 P10 M10 L10 N11 P12 N12 P13 -
Type BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL INPUT INPUT OUTPUT3 CONTROL BIDIR CONTROL INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT BIDIR CONTROL OUTPUT3 CONTROL OUTPUT3 OUTPUT3 OUTPUT3 OUTPUT3 OUTPUT3 OUTPUT3 OUTPUT3 CONTROL BIDIR CONTROL INPUT BIDIR CONTROL INPUT BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL OUTPUT3 OUTPUT3 OUTPUT3 OUTPUT3 OUTPUT3 OUTPUT3 OUTPUT3 OUTPUT3 OUTPUT3 CONTROL BIDIR CONTROL
Tri-state Control Cell 90 92 94 96 100 102 112 114 122 122 122 122 122 122 122 124 126 129 131 133 135 145 145 145 145 145 145 145 145 145 148 -
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PI7C9X110
PCIe-to-PCI Reversible Bridge
Boundary Scan Register Number 149 150 151 152 153
Pin Name REVRSB INTD_L MSK_IN IDSEL
Ball Location M12 N13 P14 N14
Type INPUT BIDIR CONTROL INPUT INPUT
Tri-state Control Cell 151 -
15
POWER MANAGEMENT
PI7C9X110 supports D0, D3-hot, D3-cold Power States. D1 and D2 states are not supported. The PCI Express Physical Link Layer of the PI7C9X110 device supports the PCI Express Link Power Management with L0, L0s, L1, L2/L3 ready and L3 Power States. For the PCI Port of PI7C9X110, it supports the standard PCI Power Management States with B0, B1, B2 and B3. During D3-hot state, the main power supplies of VDDP, VDDC, and VD33 can be turned off to save power while keeping the VDDAUX, VDDCAUX, and VAUX with the auxiliary power supplies to maintain all necessary information to be restored to the full power D0 state. PI7C9X110 has been designed to have sticky registers that are powered by auxiliary power supplies. PME_L pin allows PCI devices to request power management state changes. Along with the operating system and application software, PCI devices can achieve optimum power saving by using PME_L in forward bridge mode. PI7C9X110 converts PME_L signal information to power management messages to the upstream switches or root complex. In reverse bridge mode, PI7C9X110 converts the power management event messages from PCIe devices to the PME_L signal and continues to request power management state change to the host bridge. PI7C9X110 also supports ASPM (Active State Power Management) to facilitate the link power saving. PI7C9X110 supports beacon generation but does not support WAKE# signal.
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PI7C9X110
PCIe-to-PCI Reversible Bridge
16
ELECTRICAL AND TIMING SPECIFICATIONS
16.1 ABSOLUTE MAXIMUM RATINGS
Table 16-1 Absolute maximum ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature Ambient Temperature with power appiled PCI Express supply voltage to ground potential (VDDA, VDDP, VDDC, VDDAUX, and VDDCAUX) PCI supply voltage to ground potential (VD33 and VAUX) DC input voltage for PCI Express signals DC input voltage for PCI signals -65oC to 150oC 0oC to 85oC -0.3v to 3.0v -0.3v to 3.6v -0.3v to 3.0v -0.5v to 5.75v
Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
16.2 DC SPECIFICATIONS
Table 16-2 DC electrical characteristics
Power Pins VDDA VDDP VDDC VDDAUX VDDCAUX VTT VD33 VAUX Min. 1.6v 1.6v 1.6v 1.6v 1.6v VDDC 3.0v 3.0v Typ. 1.8v 1.8v 1.8v 1.8v 1.8v VDDC 3.3v 3.3v Max. 2.0v 2.0v 2.0v 2.0v 2.0v 2.0v 3.6v 3.6v
VDDA: analog power supply for PCI Express Interface VDDP: digital power supply for PCI Express Interface VDDAUX: digital auxiliary power supply for PCI Express Interface VTT: termination power supply for PCI Express Interface VDDC: digital power power supply for the core VDDCAUX: digital auxiliary power supply for the core VD33: digital power supply for PCI/PCI-X interface VAUX: digital auxiliary power supply for PCI/PCI-X interface In order to support auxiliary power management fully, it is recommended to have VDDP and VDDAUX separated. By the same token, VD33/VDDC and VAUX/VDDCAUX need to be separated for auxiliary power management support. However, if auxiliary power management is not required, VD33 and VDDC can be connected to VAUX and VDDCAUX respectively. The typical power consumption of PI7C9X110 is about 1.0 watt.
Page 141 of 145 Pericom Semiconductor November 2007, Revision 2.4
PI7C9X110
PCIe-to-PCI Reversible Bridge
PI7C9X110 is capable of sustaining 1500V human body model for the ESD protection without any damages.
16.3 AC SPECIFICATIONS
Table 16-3 PCI bus timing parameters
Symbol Tsu Tsu (ptp) Th Tval Tval (ptp) Ton Toff Parameter Input setup time to CLK - bused signals 1,2,3 Input setup time to CLK - point-to-point 1,2,3 Input signal hold time from CLK 1,2 CLK to signal valid delay - bused signals 1,2,3 CLK to signal valid delay - point-to-point 1,2,3 Float to active delay 1,2 Active to float delay 1,2 MIN 3 5 0 2 2 2 66 MHz MAX 6 6 14 33 MHz MIN MAX 7 10, 124 0 2 11 2 12 2 28 Units
ns
1. 2. 3. 4.
See Figure 16 -1 PCI Signal Timing Measurement Conditions. All PCI interface signals are synchronized to FBCLKIN. Point-to-point signals are REQ_L [7:0], GNT_L [7:0], LOO, and ENUM_L. Bused signals are AD, CBE, PAR, PERR_L, SERR_L, FRAME_L, IRDY_L, TRDY_L, LOCK_L, STOP_L and IDSEL. REQ_L signals have a setup of 10ns and GNT_L signals have a setup of 12ns.
Figure 16-1 PCI signal timing conditions
Page 142 of 145 Pericom Semiconductor November 2007, Revision 2.4
PI7C9X110
PCIe-to-PCI Reversible Bridge
17
PACKAGE INFORMATION
Figure 17-1 Top view drawing
Figure 17-2 Bottom view drawing
Page 143 of 145 Pericom Semiconductor November 2007, Revision 2.4
PI7C9X110
PCIe-to-PCI Reversible Bridge
The package of PI7C9X110 is a 12mm x 12mm LFBGA (160 Pin) package. The ball pitch is 0.8mm and the ball size is 0.5mm. The following are the package information and mechanical dimension: Figure 17-3 Package outline drawing
18
ORDERING INFORMATION
PART NUMBER
PI7C9X110BNBE
PIN - PACKAGE
160 - LFBGA
PB-FREE & GREEN
YES
TEMPERATURE RANGE
-40 TO +85C
Page 144 of 145 Pericom Semiconductor November 2007, Revision 2.4
PI7C9X110
PCIe-to-PCI Reversible Bridge
NOTES:
Page 145 of 145 Pericom Semiconductor November 2007, Revision 2.4

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